NB3N62208MNG ON Semiconductor

NB3Nxxxxx - VCXO Series 3.3V PureEdge VCXO Clock Generator with Differential LVPECL Outputs Description NB3Nxxxxx VCXO Series Exposed Pad Table 1. OUTPUT ENABLE TRISTATE FUNCTION nc XIN nc XOUT nc OE Output Pins Function 20 19 18 17 16 Open Active High Active Low High Z V 1 15 V C DD OE 2 14 V DD GND 3 13 V DD 4 12 GND CLK GND 5 11 CLK 67 8 9 10 nc nc nc nc nc Figure 2. QFN 20 Pinout (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 VC Analog Input Analog control voltage input pin that adjusts output oscillation frequency. f0 = V = 1.65 V. C Control voltage has a positive slope with a linearity of 10% V = 1.65 V 1 V. C 2 OE LVTTL / Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. LVCMOS Input See OE pin description Table 1. 3 GND Ground Negative Supply Voltage 4 GND Ground Negative Supply Voltage 5 GND Ground Negative Supply Voltage 6 nc No connect 7 nc No connect 8 nc No connect 9 nc No connect 10 nc No connect 11 CLK LVPECL Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V 2 V. DD 12 CLK LVPECL Output Inverted Differential Output. Typically Terminated with 50 Resistor to V 2 V. DD 13 VDD Power Supply 3.3 V Positive Supply Voltage 14 VDD Power Supply 3.3 V Positive Supply Voltage 15 VDD Power Supply 3.3 V Positive Supply Voltage 16 nc No connect 17 XOUT Crystal Crystal Input. This pin forms an oscillator when connected to an external parallel resonant crystal. 18 nc No connect 19 XIN Crystal Crystal Input. This pin forms an oscillator when connected to an external parallel resonant crystal.