74LCX157TTR STMicroelectronics

74LCX157 Low voltage CMOS Quad 2 channel multiplexer with 5V tolerant inputs Features 5V tolerant inputs High speed: t = 6.0ns (Max) at V = 3V PD CC Power down protection on inputs and outputs Symmetrical output impedance: SO-16 TSSOP16 I = I = 24mA (Min) at V = 3V OH OL CC PCI bus levels guaranteed at 24mA Description Balanced propagation delays: t t The 74LCX157 is a low voltage CMOS Quad 2 PLH PHL channel multiplexer fabricated with sub-micron Operating voltage range: 2 silicon gate and double-layer metal wiring C MOS V (Opr) = 2.0V to 3.6V CC technology. It is ideal for low power and high Pin and function compatible with speed 3.3V applications it can be interfaced to 74 series 157 5V signal environment for inputs. Latch-up performance exceeds It consists of four 2-input digital multiplexer with 500mA (JESD 17) common select and strobe inputs. It is a non- ESD performance: inverting multiplexer. When the STROBE input is held high selection of data is inhibited and all the HBM > 2000V outputs become low. The SELECT decoding (MIL STD 883 method 3015) MM > 200V determines whether the A or B inputs get routed to their corresponding Y outputs. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Order codes Part number Package Packaging 74LCX157MTR SO-16 Tape and reel 74LCX157TTR TSSOP16 Tape and reel February 2007 Rev 6 1/17 www.st.com 17Contents 74LCX157 Contents 1 Logic symbols and I/O equivalent circuit 3 2 Pin settings 4 2.1 Pin connection 4 2.2 Pin description 4 2.3 Truth table 5 2.4 Logic diagram . 5 3 Maximum rating . 6 3.1 Recommended operating conditions . 6 4 Electrical characteristics . 7 5 Test circuit . 9 6 Waveforms 10 7 Package mechanical data 11 8 Revision history . 16 2/17