DS1742 Y2KC Nonvolatile Timekeeping RAM FEATURES PIN CONFIGURATION Integrated NV SRAM, Real-Time Clock, TOP VIEW Crystal, Power-Fail Control Circuit and Lithium Energy Source 1 24 V A7 CC Clock Registers are Accessed Identically to 2 23 A8 A6 DS1742 3 22 A9 A5 the Static RAM These Registers are 4 21 WE A4 Resident in the Eight Top RAM Locations 5 20 A3 OE 6 19 A2 A10 Century Byte Register 7 18 A1 CE Totally Nonvolatile with Over 10 Years of A0 8 17 DQ7 9 16 Operation in the Absence of Power DQ0 DQ6 10 15 DQ1 DQ5 BCD Coded Century, Year, Month, Date, 11 14 DQ2 DQ4 Day, Hours, Minutes, and Seconds with 12 13 GND DQ3 Automatic Leap Year Compensation Valid ENCAPSULATED DIP Up to the year 2100 Battery Voltage Level Indicator Flag Power-Fail Write Protection Allows for 10% V Power Supply Tolerance CC Lithium Energy Source is Electrically Disconnected to Retain Freshness until Power is Applied for the First Time Standard JEDEC Bytewide 2k x 8 Static RAM Pinout Quartz Accuracy 1 Minute a Month at +25C, Factory Calibrated Underwriters Laboratories (UL) Recognized ORDERING INFORMATION PART VOLTAGE (V) TEMP RANGE PIN-PACKAGE TOP MARK** DS1742-85+ 5.0 0C to +70C 24 EDIP (0.740a) DS1742-85+ 5.0 0C to +70C DS1742-100+ 24 EDIP (0.740a) DS1742-100+ DS1742-100IND+ 5.0 -40C to +85C 24 EDIP (0.740a) DS1742-100IND+ DS1742W-120+ 3.3 0C to +70C 24 EDIP (0.740a) DS1742W-120+ DS1742W-150+ 3.3 0C to +70C 24 EDIP (0.740a) DS1742W-150+ +Denotes a lead(Pb)-free/RoHS-compliant device. **The top mark will include a + on lead(Pb)-free devices. 1 of 17 19-6715 Rev 6/13 DS1742 PIN DESCRIPTION PIN NAM33B E FUNCTION 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 Address Input 7 A1 8 A0 19 A10 22 A9 23 A8 9 DQ0 10 DQ1 11 DQ2 13 DQ3 Data Input/Output 14 DQ4 15 DQ5 16 DQ6 17 DQ7 12 GND Ground 18 CE Active-Low Chip-Enable Input 20 OE Active-Low Output-Enable Input 21 WE Active-Low Write-Enable Input 24 V Power-Supply Input CC DESCRIPTION The DS1742 is a full-function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 2k x 8 nonvolatile static RAM. User access to all registers within the DS1742 is accomplished with a bytewide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are doublebuf- fered to avoid access of incorrect data that can occur during clock update cycles. The doubufblef-ered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1742 also contains its own power-fail circuitry, which deselects the device when the V supply is in an CC out-of-tolerance condition. This feature prevents loss of data from unpablre edicstystem operation brought on by low V as errant access and update cycles are avoided. CC 2 of 17