SPI, 1.5 R , 15 V/5 V/+12 V, High ON Density Octal SPST Switch Data Sheet ADGS1414D FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD SS SPI with error detection Includes CRC, invalid read and write address, and SCLK count error detection ADGS1414D Supports burst mode and daisy-chain mode S1 D1 Industry-standard SPI Mode 0 and Mode 3 interface S2 D2 compatible S3 D3 Integrated passive components S4 D4 Route through of digital signals and supplies S5 D5 S6 D6 Guaranteed break-before-make switching allowing external S7 D7 wiring of switches to deliver multiplexer configurations S8 D8 V 1.5 typical on resistance at 25C (15 V dual supply) L 0.3 typical on resistance flatness at 25C (15 V dual supply) SPI SDO INTERFACE 0.1 typical on resistance match between channels at 25C (15 V dual supply) V to V analog signal range SS DD Fully specified at 15 V, 5 V, and +12 V SCLK SDI CS RESET/V L 1.8 V logic compatibility with 2.7 V V 3.3 V (excludes SPI L Figure 1. readback to a 1.8 V device) The ADGS1414D is suited to high density switching 4 mm 5 mm, 30-terminal LGA applications, such as large switching matrices and fanout APPLICATIONS applications. Automated test equipment Each switch conducts equally well in both directions when on, Data acquisition systems and each switch has an input signal range that extends to the Sample-and-hold systems supplies. In the off condition, signal levels up to the supplies Audio and video signal routing are blocked. Communications systems Multifunction pin names may be referenced by their relevant Relay replacement function only. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADGS1414D contains eight independent SPST switches. A 1. The SPI removes the need for parallel conversion and logic serial peripheral interface (SPI) controls the switches. The SPI traces and reduces the general-purpose input and output has robust error detection features, such as cyclic redundancy (GPIO) channel count. check (CRC) error detection, invalid read and write address 2. Daisy-chain mode removes additional logic traces when detection, and SCLK count error detection. multiple devices are used. It is possible to daisy-chain multiple ADGS1414D devices 3. Route through of digital signals and supplies eases routing together. Daisy-chain mode enables the configuration of and allows for an increase in channel density. multiple devices with a minimal amount of digital lines. The 4. Integrated passive components eliminate the need for route of digital signals and supplies through the ADGS1414D external passive components. allows for a further increase in channel density. Integrated 5. CRC error detection, invalid read and write address passive components eliminate the need for external passive detection, and SCLK count error detection ensure a robust components. digital interface. 6. CRC, invalid read and write address, and SCLK error detection capabilities allow for the use of the ADGS1414D in safety critical systems. 7. Minimum distortion. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 23895-001ADGS1414D Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Clearing the Error Flags Register ............................................. 21 Applications ...................................................................................... 1 Burst Mode .................................................................................. 21 General Description ......................................................................... 1 Software Reset ............................................................................. 21 Functional Block Diagram .............................................................. 1 Daisy-Chain Mode ..................................................................... 21 Product Highlights ........................................................................... 1 Power-On Reset .......................................................................... 22 Revision History ............................................................................... 2 Applications Information ............................................................. 23 Specifications .................................................................................... 3 System Channel Density ........................................................... 23 15 V Dual Supply ....................................................................... 3 Break-Before-Make Switching ................................................. 24 5 V Dual Supply ......................................................................... 5 Digital Input Buffers .................................................................. 24 12 V Single Supply ....................................................................... 7 Power Supply Rails ..................................................................... 24 Continuous Current per Channel, Sx or Dx ............................ 9 Power Supply Recommendations ............................................ 24 Timing Characteristics ................................................................ 9 1.8 V Logic Compatibility ......................................................... 24 Absolute Maximum Ratings ......................................................... 11 Register Summary .......................................................................... 25 Thermal Resistance .................................................................... 11 Register Details ............................................................................... 26 Electrostatic Discharge (ESD) Ratings .................................... 11 Switch Data Register .................................................................. 26 ESD Caution................................................................................ 11 Error Configuration Register ................................................... 26 Pin Configuration and Function Descriptions .......................... 12 Error Flags Register .................................................................... 27 Typical Performance Characteristics ........................................... 13 Burst Enable Register ................................................................. 27 Test Circuits .................................................................................... 17 Software Reset Register ............................................................. 27 Terminology .................................................................................... 19 Outline Dimensions ....................................................................... 28 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 28 Address Mode ............................................................................. 20 Error Detection Features ........................................................... 20 REVISION HISTORY 6/2020Revision 0: Initial Version Rev. 0 Page 2 of 28