EVALUATION KIT AVAILABLE MAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC General Description Features 4 Single-Ended or Differential Channels of The MAX11043 features 4 single-ended or differential Simultaneous-Sampling, 16-Bit ADCs channels of simultaneous-sampling ADCs with 16-bit resolution. The MAX11043 contains a versatile filter 10 LSB INL, 1 LSB DNL, No Missing Codes block and programmable-gain amplifier (PGA) per 93dB SFDR at 100kHz Input channel. The filter consists of seven cascaded 2nd- PGA with Gain of 1, 2, 4, 8, 16, 32, or 64 for order filter sections for each channel, allowing the con- Each Channel struction of a 14th-order filter. The filter coefficients are EQ Function Automatically Boosts user-programmable. Configure each 2nd-order filter as High-Frequency, Low-Amplitude Signals lowpass (LP), highpass (HP), or bandpass (BP) with Seven-Stage Internal Programmable Biquad optional rectification. Gain and phase mismatch of the Filters per Channel analog signal path is better than -50dB. High Throughput, 400ksps per Channel for 4 The ADC can digitize signals up to 200kHz. A 40MHz Channels serial interface provides communication to and from the Dual-Stage DAC device. The SPI interface provides throughput of Two 8-Bit Coarse Reference DACs 1600ksps 4 channels at 400ksps per channel or 2 12-Bit Fine DAC channels at 800ksps per channel. A software-selec- +2.5V Internal Reference or +2.0V to +2.8V table scan mode allows reading the ADC results while External Reference simultaneously updating the DAC. Other features of the Single +3.3V Operation MAX11043 include an internal (+2.5V) or external Shutdown and Power-Saving Modes (+2.0V to +2.8V) reference, power-saving modes, and a PGA with gains of 1 to 64. The PGA includes an 40-Pin, 6mm x 6mm TQFN Package equalizer (EQ) function that automatically boosts low- -40C to +125C Operating Temperature amplitude, high-frequency signals for applications such as CW-chirp radar. Ordering Information The MAX11043 includes two 8-bit coarse DACs that set PART TEMP RANGE PIN-PACKAGE the high and low references for a second-stage 12-bit MAX11043ATL+ -40C to +125C 40 TQFN-EP* fine DAC, typically used for VCO control. Use software controls to write to the DAC or step the DAC up and MAX11043ATL/V+ -40C to +125C 40 TQFN-EP* down under hardware control in programmable steps. +Denotes a lead(Pb)-free/RoHS-compliant package. The device operates from a +3.0V to +3.6V supply. The /V denotes an automotive qualified part. MAX11043 is available in a 40-pin, 6mm x 6mm TQFN *EP = Exposed pad. package and operates over the extended -40C to Pin Configuration +125C temperature range. TOP VIEW Applications 30 29 28 27 26 25 24 23 22 21 AINDN 31 20 OSCOUT Automotive Radar Systems AINDP 32 19 OSCIN Data Acquisition Systems AGND 33 18 EOC Industrial Controls 17 I.C. REFBP 34 I.C. 35 16 SCLK Power-Grid Monitoring MAX11043 15 DIN AINCN 36 AINCP 37 14 DOUT 38 13 CS REFC *EP + 39 12 CONVRUN REFB 40 11 DACSTEP AINBP 12 3 45 6 7 89 10 TQFN *CONNECT EP TO AGND. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maximintegrated.com. 19-4250 Rev 3 11/12 AINBN REFD REFA REFDAC AINAN REFDACH AINAP REFDACL AVDD AVDD AGND AOUT DGND AGND DVDD DGND DVDD DVREG UP/DWN SHDNMAX11043 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ABSOLUTE MAXIMUM RATINGS AVDD to AGND ....................................................-0.3V to +4.0V Continuous Power Dissipation (T = +70C) A DVDD to DGND.....................................................-0.3V to +4.0V TQFN Multilayer Board DVREG to DGND...................................................-0.3V to +3.0V (derate 37mW/C above +70C)................................2963mW AGND to DGND.....................................................-0.3V to +0.3V TQFN Single-Layer Board Analog I/O, REFDACH, REFDACL, REFA, REFB, REFC, REFD, (derate 26.3mW/C above +70C)..........................2105.3mW AOUT, REFDAC, REFBP to AGND.....-0.3V to (V + 0.3V) Operating Temperature Range .........................-40C to +125C AVDD UP/DWN, CONVRUN, SHDN, DACSTEP, EOC, Digital I/O, Junction Temperature......................................................+150C OSCIN, OSCOUT to DGND....................-0.3V to (V + 0.3V) Storage Temperature Range ............................-65C to +150C DVDD Maximum Current into Any Pin except AVDD, DVDD, DVREG, Lead Temperature (soldering, 10s) ................................+300C AGND, DGND...............................................................50mA Soldering Temperature (reflow) ......................................+260C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V = +3.0V to +3.6V, V = +3.0V, C = 10F, V = V = 0V, common-mode input voltage = V /2, V AVDD DVDD DVREG AGND DGND AVDD REFBP = V = V = V = V = +2.5V (external reference), V = V = +1.25V (external reference), V = REFA REFB REFC REFD REFDAC REFDACH REFDACL 0V, C = C = C = C = C = C = 1F, f = 38.4MHz, f = 38.4MHz (external clock applied to REFBP REFA REFB REFC REFD REFDAC SCLK EXCLK OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through a series 150/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. T = T to T , unless otherwise noted A MIN MAX (Note 1). Typical values are at T = +25C.) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SIGMA-DELTA ADC Resolution N 16 Bits Integral Nonlinearity INL -16 2 LSB Differential Nonlinearity DNL Guaranteed monotonic -1 +1 LSB Offset Error OE -35 +35 mV Offset-Error Drift 30 V/C Gain Error GE Trimmed with 150/330pF anti-alias filter -1 +1 % Gain Temperature Coefficient 50 ppm/C Channel Gain-Error Matching Complete analog signal path -0.25 +0.25 % Channel Offset Matching Complete analog signal path -60 +60 mV DYNAMIC PERFORMANCE (PGA Disabled, PGA Gain = 1 x (25kHz -1dB Full-Scale Signal)) Maximum Full-Scale Input ADC modulator gain = 1 1.2 V P-P Input-Referred Noise Spectral 100kHz 85 nV/Hz Density Second Harmonic to -80 -93 dB Fundamental Third Harmonic to Fundamental -80 -110 dB Spurious-Free Dynamic Range SFDR 77 93 dB Unused channels are shorted and Channel-to-Channel Isolation 85 108 dB unconnected Between all channels, including complete Channel Phase Matching -0.05 +0.05 Degrees analog signal path 2 Maxim Integrated