009
CY7C109
CY7C1009
128K x 8 Static RAM
active HIGH chip enable (CE ), an active LOW output enable
Features
2
(OE), and three-state drivers. Writing to the device is accom-
High speed plished by taking chip enable one (CE ) and write enable (WE)
1
inputs LOW and chip enable two (CE ) input HIGH. Data on
2
t = 10 ns
AA
the eight I/O pins (I/O through I/O ) is then written into the
0 7
Low active power
location specified on the address pins (A through A ).
0 16
1017 mW (max., 12 ns)
Reading from the device is accomplished by taking chip en-
Low CMOS standby power
able one (CE ) and output enable (OE) LOW while forcing
1
55 mW (max.), 4 mW (Low power version) write enable (WE) and chip enable two (CE ) HIGH. Under
2
these conditions, the contents of the memory location speci-
2.0V Data Retention (Low power version)
fied by the address pins will appear on the I/O pins.
Automatic power-down when deselected
The eight input/output pins (I/O through I/O ) are placed in a
0 7
TTL-compatible inputs and outputs
high-impedance state when the device is deselected (CE
1
Easy memory expansion with CE , CE , and OE options
1 2
HIGH or CE LOW), the outputs are disabled (OE HIGH), or
2
during a write operation (CE LOW, CE HIGH, and WE LOW).
1 2
Functional Description
The CY7C109 is available in standard 400-mil-wide SOJ and
The CY7C109 / CY7C1009 is a high-performance CMOS stat- 32-pin TSOP type I packages. The CY7C1009 is available in
ic RAM organized as 131,072 words by 8 bits. Easy memory
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
expansion is provided by an active LOW chip enable (CE ), an
are functionally equivalent in all other respects.
1
Logic Block Diagram Pin Configurations
SOJ
Top View
V
NC 1 32
CC
A
16 31 A
2
15
A 30
14 3 CE
2
A
12 4 29 WE
28
A 5 A
7 13
27
A
6 6 A
8
26
A
5 7 A
9
A 25
8 A
4
11
A 24
3 9
OE
I/O A 23
10 A
0 2 10
A
22 CE
INPUT BUFFER 1 11
1
I/O
A 21 7
12
0
I/O I/O I/O
0 20 6
1 13
A
0
I/O I/O
1 19 5
14
A
1
I/O I/O
2 15 18 4
I/O
A 2
2
GND 17 I/O
16 3
1092
A
3
A A 1
4 11 32 OE
I/O
3
512x256 x8
2
A 31
A
A 9
5 10
ARRAY
A 3
30 CE
8
A
6
4
A 29
I/O 13 I/O
7
4
A
7 5
28
WE I/O
6
A
8 CE 6 27
I/O
2
5
A 7
I/O 26
5 15 TSOP I I/O
4
V 8 25 I/O
Top View
CC 3
24
NC 9 GND
(not to scale)
A 23 I/O
I/O 16 10 2
6
POWER
22 I/O
COLUMN A 11
14 1
CE DOWN
1
A 21 I/O
DECODER 12
12 0
CE
2
A 13 20 A
I/O 7 0
WE 7
A 19 A
14 1
6
18 A
A 15 2
5
1091
17 A
16
OE A 3
4
1093
Selection Guide
7C109-10 7C109-12 7C109-15 7C109-20 7C109-25 7C109-35
7C1009-10 7C1009-12 7C1009-15 7C1009-20 7C1009-25 7C1009-35
Maximum Access Time (ns) 10 12 15 20 25 35
Maximum Operating Current (mA) 195 185 155 140 135 125
Maximum CMOS Standby Current (mA) 10 10 10 10 10 10
Maximum CMOS Standby Current (mA) 2 2 2
Low Power Version
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation 3901NorthFirstStreet San Jose CA 95134 408-943-2600
Document #: 38-05032 Rev. ** Revised August 24, 2001
ROW DECODER
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SENSE AMPS
CY7C109
CY7C1009
Static Discharge Voltage ........................................... >2001V
Maximum Ratings
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................65C to +150C
Operating Range
Ambient Temperature with
Power Applied............................................. 55C to +125C
Ambient
[2]
[1]
Range Temperature V
Supply Voltage on V to Relative GND .... 0.5V to +7.0V CC
CC
Commercial 0C to +70C 5V 10%
DC Voltage Applied to Outputs
[1]
in High Z State ....................................0.5V to V + 0.5V
CC
Industrial 40C to +85C 5V 10%
[1]
DC Input Voltage ................................0.5V to V + 0.5V
CC
Current into Outputs (LOW).........................................20 mA
[3]
Electrical Characteristics Over the Operating Range
7C109-10 7C109-12 7C109-15
7C1009-10 7C1009-12 7C100915
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit
V Output HIGH Voltage V = Min., 2.4 2.4 2.4 V
OH CC
I = 4.0 mA
OH
V Output LOW Voltage V = Min., 0.4 0.4 0.4 V
OL CC
I = 8.0 mA
OL
V Input HIGH Voltage 2.2 V 2.2 V 2.2 V V
IH CC CC CC
+ 0.3 + 0.3 + 0.3
[1]
V Input LOW Voltage 0.3 0.8 0.3 0.8 0.3 0.8 V
IL
I Input Load Current GND < V < V 1 +1 1+1 1+1 A
IX I CC
I Output Leakage GND < V < V , 5 +5 5+5 5+5 A
OZ I CC
Current Output Disabled
I Output Short V = Max., 300 300 300 mA
OS CC
[3]
Circuit Current V = GND
OUT
I V Operating V = Max., 195 185 155 mA
CC CC CC
Supply Current I = 0 mA,
OUT
f = f = 1/t
MAX RC
I Automatic CE Max. V , CE > V 45 45 40 mA
SB1 CC 1 IH
Power-Down Current or CE < V ,
2 IL
TTL Inputs V > V or
IN IH
V < V , f = f
IN IL MAX
I Automatic CE Max. V , 10 10 10 mA
SB2 CC
Power-Down Current CE > V 0.3V,
1 CC
L 22 2
CMOS Inputs or CE < 0.3V,
2
V > V 0.3V,
IN CC
or V < 0.3V, f=0
IN
Shaded areas contain preliminary information.
Document #: 38-05032 Rev. ** Page 2 of 12