CY7C130, CY7C130A
CY7C131, CY7C131A
1 K 8 Dual-Port Static RAM
1 K 8 Dual-Port Static RAM
Features Functional Description
[1]
True dual-ported memory cells, which allow simultaneous The CY7C130/130A/CY7C131/131A/CY7C140 and CY7C141
reads of the same memory location are high speed CMOS 1 K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
1 K 8 organization
memory. The CY7C130/130A/CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
0.65 micron CMOS for optimum speed and power
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
High speed access: 15 ns
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
Low operating power: I = 110 mA (maximum)
CC
buffered data, such as cache memory for DSP, bit-slice, or multi-
Fully asynchronous operation processor designs.
Each port has independent control pins; chip enable (CE), write
Automatic power-down
enable (R/W), and output enable (OE). Two flags are provided
Master CY7C130/130A/CY7C131/131A easily expands data
on each port, BUSY and INT. BUSY signals that the port is trying
bus width to 16 or more bits using slave CY7C140/CY7C141
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
in a unique location (3FF for the left port and 3FE for the right
input on CY7C140/CY7C141
port). An automatic power down feature is controlled
INT flag for port-to-port communication independently on each port by the chip enable (CE) pins.
The CY7C130/130A and CY7C140 are available in 48-pin DIP.
Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
The CY7C131/131A and CY7C141 are available in 52-pin
52-pin TQFP
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
Pb-free packages available
PQFP.
Logic Block Diagram
R/W
L
R/W
R
CE
L
CE
R
OE
L OE
R
I/O
I/O
7L
7R
I/O I/O
CONTROL CONTROL
I/O
I/O 0R
0L
[2]
BUSY BUSY
L R
A A
9L 9R
MEMORY
ADDRESS ADDRESS
ARRAY
DECODER
DECODER
A A
0L 0R
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
CE
L CE
R
AND
INTERRUPT LOGIC
OE
L OE
R
R/W R/W
L R
[3]
[3]
INT INT
L R
Notes
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.
2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.
CY7C140/CY7C141 (Slave): BUSY is input.
3. Open drain outputs: pull-up resistor required.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-06002 Rev. *H Revised October 12, 2011CY7C130, CY7C130A
CY7C131, CY7C131A
Contents
Pin Configurations ...........................................................3 Ordering Information ...................................................... 17
Pin Definitions ..................................................................4 Ordering Code Definitions ......................................... 17
Selection Guide ................................................................4 Package Diagrams .......................................................... 18
Maximum Ratings .............................................................5 Acronyms ........................................................................20
Operating Range ...............................................................5 Document Conventions ................................................. 20
Electrical Characteristics .................................................5 Units of Measure ....................................................... 20
Capacitance ......................................................................6 Document History Page ................................................. 21
Switching Characteristics ................................................7 Sales, Solutions, and Legal Information ...................... 22
Switching Characteristics ................................................9 Worldwide Sales and Design Support ....................... 22
Switching Waveforms ....................................................11 Products ....................................................................22
Typical DC and AC Characteristics ..............................16 PSoC Solutions ......................................................... 22
Document Number: 38-06002 Rev. *H Page 2 of 22