CY7C1325H 4-Mbit (256K 18) Flow-Through Sync SRAM 4-Mbit (256K 18) Flow-Through Sync SRAM 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the Features first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated 256K 18 common I/O by registers controlled by a positive-edge-triggered Clock Input 3.3 V core power supply (V ) DD (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE ), depth-expansion 1 2.5 V or 3.3 V I/O power supply (V ) DDQ chip enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 Fast clock-to-output times and ADV), write enables (BW , and BWE), and global write A:B (GW). Asynchronous inputs include the output enable (OE) and 6.5 ns (133 MHz version) the ZZ pin. Provide high performance 2-1-1-1 access rate The CY7C1325H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an User selectable burst counter supporting Intel Pentium interleaved burst sequence, while a LOW selects a linear burst interleaved or linear burst sequences sequence. Burst accesses can be initiated with the processor Separate processor and controller address strobes address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Synchronous self timed write Addresses and chip enables are registered at rising edge of Asynchronous output enable clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst Available in Pb-free 100-pin TQFP package addresses can be internally generated as controlled by the ZZ sleep mode option advance pin (ADV). The CY7C1325H operates from a +3.3 V core power supply Functional Description while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard The CY7C1325H is a 256K 18 synchronous cache RAM JESD8-5-compatible. designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is For a complete list of related documentation, click here. Logic Block Diagram ADDRESS A 0,A1,A REGISTER A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ B,DQP B DQ B,DQP B WRITE REGISTER WRITE DRIVER BW B MEMORY OUTPUT DQs SENSE ARRAY BUFFERS AMPS DQP A DQ A,DQP A DQP B DQ A,DQP A WRITE DRIVER BW A WRITE REGISTER BWE INPUT GW REGISTERS ENABLE CE 1 REGISTER CE 2 CE 3 OE SLEEP ZZ CONTROL Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-86114 Rev. *D Revised June 23, 2016CY7C1325H Contents Selection Guide ................................................................3 Capacitance ....................................................................10 Pin Configurations ...........................................................3 Thermal Resistance ........................................................ 10 Pin Definitions ..................................................................4 AC Test Loads and Waveforms ..................................... 11 Functional Overview ........................................................5 Switching Characteristics .............................................. 12 Single Read Accesses ................................................5 Timing Diagrams ............................................................ 13 Single Write Accesses Initiated by ADSP ...................5 Ordering Information ...................................................... 17 Single Write Accesses Initiated by ADSC ...................5 Ordering Code Definitions ......................................... 17 Burst Sequences .........................................................5 Package Diagrams .......................................................... 18 Sleep Mode .................................................................5 Acronyms ........................................................................19 Interleaved Burst Address Table .................................6 Document Conventions ................................................. 19 Linear Burst Address Table .........................................6 Units of Measure ....................................................... 19 ZZ Mode Electrical Characteristics ..............................6 Document History Page ................................................. 20 Truth Table ........................................................................7 Sales, Solutions, and Legal Information ...................... 21 Truth Table for Read/Write ..............................................8 Worldwide Sales and Design Support ....................... 21 Maximum Ratings .............................................................9 Products ....................................................................21 Operating Range ...............................................................9 PSoCSolutions .......................................................21 Neutron Soft Error Immunity ...........................................9 Cypress Developer Community ................................. 21 Electrical Characteristics .................................................9 Technical Support ..................................................... 21 Document Number: 001-86114 Rev. *D Page 2 of 21