CY7C1328G 4-Mbit (256 K 18) Pipelined DCD Sync SRAM 4-Mbit (256 K 18) Pipelined DCD Sync SRAM Features Functional Description Registered inputs and outputs for pipelined operation The CY7C1328G SRAM integrates 256 K 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter Optimal for performance (double-cycle deselect) for internal burst operation. All synchronous inputs are gated by Depth expansion without wait state registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data 256 K 18 common I/O architecture inputs, address-pipelining chip enable (CE ), depth-expansion 1 3.3 V core power supply (V ) chip enables (CE and CE ), burst control inputs (ADSC, ADSP, DD 2 3 ADV), write enables (BW , and BWE), and global write and A:B 3.3 V/2.5 V I/O power supply (V ) DDQ (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Fast clock-to-output times 4.0 ns (for 133-MHz device) Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address Provide high-performance 3-1-1-1 access rate strobe controller (ADSC) are active. Subsequent burst User-selectable burst counter supporting Intel Pentium addresses can be internally generated as controlled by the interleaved or linear burst sequences advance pin (ADV). Address, data inputs, and write controls are registered on-chip Separate processor and controller address strobes to initiate a self-timed write cycle.This part supports byte write Synchronous self-timed writes operations (see Pin Definitions on page 5 and Truth Table on page 8 for further details). Write cycles can be one to two bytes Asynchronous output enable wide as controlled by the byte write control inputs. GW active Available in Pb-free 100-pin TQFP package LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the ZZ sleep mode option output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The CY7C1328G operates from a +3.3 V core power supply while all outputs operate with a +3.3 V or a +2.5 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide Description 133 MHz Unit Maximum access time 4.0 ns Maximum operating current 225 mA Maximum CMOS standby current 40 mA Errata: For information on silicon errata, see Errata on page 20. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05523 Rev. *O Revised November 18, 2014CY7C1328G Logic Block Diagram ADDRESS A0, A1, A REGISTER 2 A 1:0 MODE Q1 ADV BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB , DQPB DQB, DQPB BYTE BYTE WRITE DRIVER OUTPUT BWB OUTPUT DQs, WRITE REGISTER SENSE MEMORY BUFFERS REGISTERS DQPA AMPS ARRAY DQA, DQPA DQPB E DQA , DQPA BYTE BYTE BWA WRITE DRIVER WRITE REGISTER BWE INPUT GW ENABLE REGISTERS CE1 PIPELINED REGISTER CE2 ENABLE CE3 OE SLEEP ZZ CONTROL Document Number: 38-05523 Rev. *O Page 2 of 23