CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
2K x 8 Dual-Port Static RAM
Features Functional Description
True dual-ported memory cells that enable simultaneous reads The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146
of the same memory location are high speed CMOS 2K x 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
2K x 8 organization
memory. The CY7C132, CY7C136, and CY7C136A can be used
as either a standalone 8-bit dual-port static RAM or as a
0.65 micron CMOS for optimum speed and power
MASTER dual-port RAM, in conjunction with the
High speed access: 15 ns
CY7C142/CY7C146 SLAVE dual-port device. They are used in
systems that require 16-bit or greater word widths. This is the
Low operating power: I = 110 mA (maximum)
CC
solution to applications that require shared or buffered data, such
Fully asynchronous operation as cache memory for DSP, bit-slice, or multiprocessor designs.
Each port has independent control pins; chip enable (CE), write
Automatic power down
enable (R/W), and output enable (OE). BUSY flags are provided
[1]
Master CY7C132/CY7C136/CY7C136A easily expands data
on each port. In addition, an interrupt flag (INT) is provided on
bus width to 16 or more bits using slave CY7C142/CY7C146
each port of the 52-pin PLCC version. BUSY signals that the port
is trying to access the same location currently being accessed
BUSY output flag on CY7C132/CY7C136/CY7C136A;
by the other port. On the PLCC version, INT is an interrupt flag
BUSY input on CY7C142/CY7C146
indicating that data is placed in an unique location (7FF for the
left port and 7FE for the right port).
INT flag for port to port communication (52-Pin PLCC/PQFP
versions)
An automatic power down feature is controlled independently on
each port by the chip enable (CE) pins.
CY7C136, CY7C136A, and CY7C146 available in 52-pin
PLCC and 52-pin PQFP packages
Pb-free packages available
Logic Block Diagram
R/W
L R/W
R
CE
L
CE
R
OE
L OE
R
I/O
7L I/O
7R
I/O
I/O
CONTROL CONTROL
I/O
I/O 0R
0L
[2]
[2]
BUSY BUSY
L R
A
A
10L
10R
MEMORY
ADDRESS ADDRESS
ARRAY
DECODER
DECODER
A A
0L
0R
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
CE
L CE
R
INTERRUPTLOGIC
(7C136/7C146ONLY)
OE
L OE
R
R/W R/W
L R
[3]
[3]
INT INT
L R
Notes
1. CY7C136 and CY7C136A are functionally identical.
2. CY7C132/CY7C136/CY7C136A (Master): BUSY is open drain output and requires pull up resistor. CY7C142/CY7C146 (Slave): BUSY is input.
3. Open drain outputs; pull up resistor required.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-06031 Rev. *E Revised March 24, 2009
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Pinouts
Figure 1. 52-Pin PLCC (Top View) Figure 2. 52-Pin PQFP (Top View)
7 6 5 4 3 2 1 52 51 50 49 48 47
52 51 50 49 48 47 46 45 44 43 42 41 40
A
1L OE A
8 46 R 1L OE
1 39 R
A
2L A A A
9 45 0R 2L 2 38 0R
A A A
3L 10 44 A
1R 3L 3 37 1R
A
4L A A A
11 43 4L 4 36
2R 2R
A
5L A A A
12 42 3R 5L 5 35 3R
A
6L A A
13 41 A 6L 6 34 4R
4R
7C136/7C136A 7C136/7C136A
A A
7L A A 5R
14 40 5R 7L 7 33
7C146 7C146
A A
A
8L 15 39 A 8L 8 32 6R
6R
A A A
9L A 9L 7R
16 38 7R 9 31
I/O I/O A
0L 17 37 A 0L 8R
8R 10 30
I/O I/O A
A
1L 18 36 1L 11 29 9R
9R
I/O I/O NC
2L NC 2L
19 35 12 28
I/O
I/O
3L I/O
3L 20 34 I/O 13 27 7R
7R
2122 23 24 25 26 27 28 29 30 31 32 33
1415 16 17 18 19 20 21 22 23 24 25 26
Selection Guide
7C132-55
[4]
7C132-25 7C132-30 7C132-35 7C132-45
7C136-55
[4]
7C136-15 7C136-25 7C136-30 7C136-35 7C136-45
Specification 7C136A-55 Unit
7C146-15 7C142-25 7C142-30 7C142-35 7C142-45
7C142-55
7C146-25 7C146-30 7C146-35 7C146-45
7C146-55
Maximum Access Time 15 25 30 35 45 55 ns
Maximum Operating Current Coml/Ind 190 170 170 120 120 110 mA
75 65 65 45 45 35 mA
Maximum Standby Current Coml/Ind
Shaded areas contain preliminary information.
Note:
4. 15 ns and 25 ns version available in PQFP and PLCC packages only.
Document #: 38-06031 Rev. *E Page 2 of 15
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I/O
A
4L
0L
I/O
5L OE
L
A
I/O
6L 10L
I/O
INT
7L
L
NC
BUSY
L
GND
R/W
L
I/O CE
0R L
V
I/O
CC
1R
CE
I/O R
2R
R/W
I/O
R
3R
I/O
BUSY
4R
R
I/O
INT
5R
R
I/O
A
6R
10R
A
I/O
0L
4L
I/O
OE
5L L
A
I/O
10L
6L
INT
I/O
L
7L
BUSY
NC
L
R/W
GND
L
CE
I/O
L
0R
V
CC
I/O
1R
CE
R
I/O
2R
R/W
R
I/O
3R
I/O BUSY
4R R
I/O INT
R
5R
A
I/O
10R
6R