CY7C185 64-Kbit (8 K 8) Static RAM Features Functional Description 1 High speed The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is 15 ns provided by an active LOW chip enable (CE ), an active HIGH 1 Fast t DOE chip enable (CE ), and active LOW output enable (OE) and 2 tri-state drivers. This device has an automatic power-down Low active power feature (CE or CE ), reducing the power consumption by 70% 1 2 715 mW when deselected. The CY7C185 is in a standard 300-mil-wide Low standby power DIP, SOJ, or SOIC package. 85 mW An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE 1 CMOS for optimum speed/power inputs are both LOW and CE is HIGH, data on the eight data 2 Easy memory expansion with CE , CE and OE features input/output pins (I/O through I/O ) is written into the memory 1 2 0 7 location addressed by the address present on the address pins TTL-compatible inputs and outputs (A through A ). Reading the device is accomplished by 0 12 selecting the device and enabling the outputs, CE and OE Automatic power-down when deselected 1 active LOW, CE active HIGH, while WE remains inactive or 2 Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin HIGH. Under these conditions, the contents of the location (300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded addressed by the information on address pins are present on the DIP eight data input or output pins. The input or output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity. For a complete list of related documentation, click here. Logic Block Diagram I/O 0 INPUT BUFFER I/O 1 A I/O 1 2 A 2 A 3 I/O 3 A 8K x 8 4 ARRAY A 5 I/O 4 A 6 A 7 I/O A 5 8 I/O 6 POWER CE 1 I/O DOWN 7 CE COLUMN DECODER 2 WE OE Note 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05043 Rev. *G Revised November 26, 2014 ROW DECODER A 0 A 9 A 10 A 11 A 12 SENSE AMPSCY7C185 Contents Pin Configuration .............................................................3 Package Diagrams .......................................................... 13 Selection Guide ................................................................3 Acronyms ........................................................................16 Maximum Ratings .............................................................4 Document Conventions ................................................. 16 Operating Range ...............................................................4 Units of Measure ....................................................... 16 Electrical Characteristics .................................................4 Document History Page ................................................. 17 Capacitance ......................................................................5 Sales, Solutions, and Legal Information ...................... 18 AC Test Loads and Waveforms .......................................5 Worldwide Sales and Design Support ....................... 18 Switching Characteristics ................................................6 Products ....................................................................18 Switching Waveforms ......................................................7 PSoC Solutions ...................................................... 18 Typical DC and AC Characteristics ..............................10 Cypress Developer Community ................................. 18 Truth Table ......................................................................11 Technical Support ..................................................... 18 Address Designators .....................................................11 Ordering Information ......................................................12 Ordering Code Definitions .........................................12 Document Number: 38-05043 Rev. *G Page 2 of 18