2.5 V/3.3 V SiGe Differential Smart Gate with Output Level Select NB7L86A The NB7L86A is a multifunction differential Logic Gate which www.onsemi.com can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm family of high performance Silicon Germanium products. The device is housed in a 3 x 3 mm 16 pin QFN package. Differential inputs incorporate internal 50 termination resistors 1 and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The Output Level Select (OLS) QFN16 3x3, 0.5P input is used to program the peaktopeak output amplitude between 0 CASE 485G and 800 mV in five discrete steps. The NB7L86A employs input default circuitry so that under open input condition (Dx, Dx, VTDx, VTDx, VTSEL) the Outputs of the MARKING DIAGRAM device remains stable. 1 NB7L Features 86A Maximum Input Clock Frequency > 8 GHz Typical ALYW Maximum Input Data Rate > 8 Gb/s Typical 165 ps Typical Propagation Delay 40 ps Typical Rise and Fall Times A = Assembly Location Selectable Swing PECL Output with Operating Range: L = Wafer Lot V = 2.375 V to 3.465 V with V = 0 V Y = Year CC EE W = Work Week Selectable Swing NECL Output with NECL Inputs with Operating = PbFree Package Range: V = 0 V with V = 2.375 V to 3.465 V CC EE (Note: Microdot may be in either location) Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV PeaktoPeak Output) 50 Internal Input Termination Resistors ORDERING INFORMATION This is a PbFree Device See detailed ordering and shipping information on page 17 of this data sheet. Semiconductor Components Industries, LLC, 2019 1 Publication Order Number: December, 2019 Rev. 0 NB7L86A/DNB7L86A VTD0 D0 D0 VTD0 16 15 14 13 1 V OLS 12 EE 2 11 SEL Q Exposed Pad EP 3 Q SEL 10 4 9 VTSEL V CC 8 5 6 7 VTD1 D1 D1 VTD1 Figure 1. QFN16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 OLS (Note 3) Input Input for OLS (Output Level Select) Pin. Refer Table 2 2 SEL Input: LVCMOS/LVTTL, Input for Select Logic Pin, Single Ended or Inverted Differential ECL/CML/LVDS 3 SEL Input for Select Logic Pin, Single Ended or non Inverted Differential Input: LVCMOS/LVTTL, ECL/CML/LVDS 4 VTSEL (Note 1) Pin with a common internal 50 termination from SEL/SEL Pins. Refer Table 7 for usage with different Interface options 5 VTD1 (Note 1) Pin with an internal 50 termination from D1 Pin. Refer Table 7 for usage with different Interface options 6 D1 Input: LVCMOS/LVTTL, Input Pin, Noninverted Differential or Single Ended with internal 75 k ECL/CML/LVDS connected to V EE 7 D1 Input: LVCMOS/LVTTL, Input Pin, Inverted Differential or Single Ended with internal 75 k ECL/CML/LVDS connected to V and 36.5 k connected to V EE CC 8 VTD1 (Note 1) Pin with an internal 50 termination from D1 Pin. Refer Table 7 for usage with different Interface options 9 V (Note 2) Positive Supply Voltage CC 10 Q Output: Reduced Swing ECL Output Pin, noninverted Differential Output with typical 50 termination to V = V 2 V TT CC 11 Q Output: Reduced Swing ECL Output Pin, inverted Differential Output with typical 50 termination to V = V 2 V TT CC 12 V (Note 2) Negative Supply Voltage EE 13 VTD0 (Note 1) Pin with an internal 50 termination from D0 Pin. Refer Table 7 for usage with different Interface options 14 D0 Input: LVCMOS/LVTTL, Input Pin, Inverted Differential or Single Ended with internal 75 k ECL/CML/LVDS connected to V and 36.5 k connected to V EE CC 15 D0 Input: LVCMOS/LVTTL, Input Pin, Noninverted Differential or Single Ended with internal 75 k ECL/CML/LVDS connected to V EE 16 VTD0 (Note 1) Pin with an internal 50 termination from D0 Pin. Refer Table 7 for usage with different Interface options EP Exposed Pad (EP) is thermally connected to the die for improved heat transfer out of the package. The exposed pad can be connected electrically to V on the PCB board EE 1. In the differential configuration when the input termination pins (VTD0/1, VTD0/1, VTSEL) are connected to a common termination voltage, or left open, and if no signal is applied then the device will be susceptible to selfoscillation. 2. All V and V pins must be externally connected to Power Supply to guarantee proper operation. CC EE 3. When an output level of 400 mV is desired and V V > 3.0 V, 2 k resistor should be connected from OLS pin to V . CC EE EE www.onsemi.com 2