STM32H7B0xB Datasheet 32-bit Arm Cortex -M7 280 MHz MCUs, 128-Kbyte Flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto Features FBGA Includes ST state-of-the-art patented technology Core LQFP64 UFBGA169 32-bit Arm Cortex -M7 core with double-precision FPU and L1 cache: (10 x 10 mm) (7 x 7 mm) LQFP100 UFBGA176+25 16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache (14 x 14 mm) (10x10 mm) LQFP144 line in a single access from the 128-bit embedded Flash memory frequency (20x20 mm) LQFP176 up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP (24 x 24 mm) instructions Memories 128 Kbytes of Flash memory plus 1 Kbyte of OTP memory ~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain 2x Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing and support for serial PSRAM/NOR, Hyper RAM/Flash frame formats, running up to 140 MHz in SRD mode and up to 110 MHz in DTR mode Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, NOR Flash memory clocked up to 125 MHz in Synchronous mode SDRAM/LPSDR SDRAM 8/16-bit NAND Flash memories CRC calculation unit Product summary Security ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access STM32H7B0AB, mode STM32H7B0IB, STM32H7B0xB STM32H7B0RB, General-purpose input/outputs STM32H7B0ZB, STM32H7B0VB Up to 138 I/O ports with interrupt capability Fast I/Os capable of up to 133 MHz Up to 164 5-V-tolerant I/Os Low-power consumption Stop: down to 32 A with full RAM retention Standby: 2.8 A (Backup SRAM OFF, RTC/LSE ON, PDR OFF) V : 0.8 A (RTC and LSE ON) BAT Clock management Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI External oscillators: 4-50 MHz HSE, 32.768 kHz LSE 3 PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode DS13196 - Rev 6 - May 2021 www.st.com For further information contact your local STMicroelectronics sales office.STM32H7B0xB Reset and power management 2 separate power domains, which can be independently clock gated to maximize power efficiency: CPU domain (CD) for Arm Cortex core and its peripherals, which can be independently switched in Retention mode Smart run domain (SRD) for reset and clock control, power management and some peripherals 1.62 to 3.6 V application supply and I/Os POR, PDR, PVD and BOR Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs Dedicated SDMMC power supply High power efficiency SMPS step-down converter regulator to directly supply V or an external circuitry CORE Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry Voltage scaling in Run and Stop mode Backup regulator (~0.9 V) Low-power modes: Sleep, Stop and Standby V battery operating mode with charging capability BAT CPU and domain power state monitoring pins Interconnect matrix 3 bus matrices (1 AXI and 2 AHB) Bridges (5 AHB2APB, 3 AXI2AHB) 5 DMA controllers to unload the CPU 1 high-speed general-purpose master direct memory access controller (MDMA) 2 dual-port DMAs with FIFO and request router capabilities 1 basic DMA with request router capabilities 1x basic DMA dedicated to DFSDM Up to 35 communication peripherals 4 I2C FM+ interfaces (SMBus/PMBus) 5 USART/5x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1x LPUART 6 SPIs, including 4 with muxed full-duplex I2S audio class accuracy via internal audio PLL or external clock and 1 x SPI/I2S in LP domain (up to 125 MHz) 2x SAIs (serial audio interface) SPDIFRX interface SWPMI single-wire protocol master interface MDIO Slave interface 2 SD/SDIO/MMC interfaces (up to 133 MHz) 2 CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) 1 USB OTG interfaces (1HS/FS) HDMI-CEC 8- to 14-bit camera interface up to 80 MHz 8-/16-bit parallel synchronous data input/output slave interface (PSSI) DS13196 - Rev 6 page 2/199