S-25A010A/020A/040A FOR AUTOMOTIVE 125C OPERATION 2 www.ablic.com SPI SERIAL E PROM www.ablicinc.com ABLIC Inc., 2008-2014 Rev.5.2 02 2 This IC is a SPI serial E PROM which operates under the high temperature, at high speed, with the wide range operation for automotive components. This IC has the capacity of 1 K-bit, 2 K-bit, 4 K-bit and the organization of 128 words 8-bit, 256 words 8-bit, 512 words 8-bit. Page write and Sequential read are available. Caution Before using the product in automobile control unit or medical equipment, contact to ABLIC Inc. is indispensable. Features Packages Operating voltage range 8-Pin SOP (JEDEC) Read: 2.5 V to 5.5 V 5 Write: 2.5 V to 5.5 V Operation frequency: 6.5 MHz max. 8 Write time: 4.0 ms max. 4 SPI mode (0, 0) and (1, 1) 1 Page write: 16 bytes / page Sequential read Write protect: Software, Hardware (5.0 6.0 t1.75 mm) Protect area: 25%, 50%, 100% Monitoring of a write memory state by the status register Function to prevent malfunction by monitoring clock pulse 8-Pin TSSOP Write protect function during the low power supply voltage 5 CMOS schmitt input ( CS , SCK, SI, WP , HOLD ) 8 *1 6 *2 Endurance : 10 cycle / word (Ta = 25C) 5 *2 4 5 10 cycle / word (Ta = 125C) 1 Data retention: 100 years (Ta = 25C) 50 years (Ta = 125C) (3.0 6.4 t1.1 mm) Memory capacity S-25A010A: 1 K-bit S-25A020A: 2 K-bit TMSOP-8 S-25A040A: 4 K-bit Initial delivery state: FFh, BP1 = 0, BP0 = 0 5 Burn-in specification: Wafer level burn-in 8 Operation temperature range: Ta = 40C to 125C 4 *3 Lead-free (Sn 100%), halogen-free *4 1 AEC-Q100 qualified (2.9 4.0 t0.8 mm) *1. Refer to Enduranc for details. *2. For each address (Word: 8-bit) *3. Refer to Product Name Structur for details. *4. Contact our sales office for details. Remark Refer to3. Product name lis in Product Name Structur for details of package and product. 1 X Decoder Input Control Circuit 2 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E PROM S-25A010A/020A/040A Rev.5.2 02 Block Diagram Step-up Circuit Voltage Detector Page Latch CS Clock Counter Memory SCK Mode Cell SI Decoder Array HOLD Data Register WP Status Memory Cell Array Y Decoder Address Register Status Register Output SO Control Read Circuit Circuit VCC GND Figure 1 2