EP2500ETTSL-48.000M Abracon

EP25 Series REGULATORY COMPLIANCE 2011/65 + 191 SVHC 2015/863 ITEM DESCRIPTION Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD) ELECTRICAL SPECIFICATIONS Nominal Frequency 1MHz to 125MHz Frequency Tolerance/Stability Inclusive of all conditions: Calibration Tolerance at 25C, Frequency Stability over the Operating Temperature Range,Supply Voltage Change, Output Load Change, First Year Aging at 25C, Shock, and Vibration 100ppm Maximum 50ppm Maximum Aging at 25C 5ppm/year Maximum Operating Temperature Range -20C to +70C -40C to +85C Supply Voltage 5.0Vdc 10% Input Current Unloaded 45mA Maximum Output Voltage Logic High (V ) IOH = -16mA OH Vdd-0.4Vdc Minimum at Output Logic Type of CMOS 2.4Vdc Minimum at Output Logic Type of TTL Output Voltage Logic Low (V ) IOL = +16mA OL 0.4Vdc Maximum Rise/Fall Time 4nSec Maximum (Measured at 20% to 80% of waveform) at Output Logic Type of CMOS 4nSec Maximum (Measured at 0.8Vdc to 2.0Vdc) at Output Logic Type of TTL Duty Cycle Measured at 1.4Vdc with TTL Load or 50% of waveform with HCMOS Load 50 10(%) 50 5(%) (Not available with TTL Output Logic Type over Nominal Frequency range of 27.000001MHz to 125MHz Not available with CMOS Output Logic Type over Nominal Frequency range of 50.000001MHz to 125MHz) Load Drive Capability 50pF HCMOS Load Maximum (over 1MHz to 50MHz at CMOS Output Logic Type) 15pF HCMOS Load Maximum (over 50.000001MHz to 125MHz at CMOS Output Logic Type) 10TTL Load Maximum over 1MHz to 40MHz at TTL Output Logic Type 5TTL Load Maximum over 40.000001MHz to 125MHz at TTL Output Logic Type Output Logic Type CMOS TTL Pin 1 Connection Power Down (Disabled Output: Logic Low) Tri-State (Disabled Output: High Impedance) Pin 1 Input Voltage (Vih and Vil) +2.0Vdc Minimum to enable output, +0.8Vdc Maximum to disable output, No Connect to enable output. Standby Current 50A Maximum (Pin 1 = Ground, Disabled Output: Logic Low) Disable Current 30mA Maximum (Pin 1 = Ground, Disabled Output: High Impedance) Absolute Clock Jitter 250pSec Maximum, 100pSec Typical over Nominal Frequency of 1MHz to 33MHz 100pSec Maximum, 50pSec Typical over Nominal Frequency of 33.000001MHz to 125MHz One Sigma Clock Period Jitter 50pSec Maximum over Nominal Frequency of 1MHz to 33MHz 30pSec Maximum over Nominal Frequency of 33.000001MHz to 125MHz Start Up Time 10mSec Maximum Storage Temperature Range -55C to +125C Revised H: 3/25/2014 Page 1 of 9 www.ecliptek.com EP25 Series PART NUMBERING GUIDE Revised H: 3/25/2014 Page 2 of 9 www.ecliptek.com