INTRODUCTION PIERCE ANALYZER SYSTEM (PAS) ADVANCED BOARD CHARACTERIZATION SERVICE Todays electronic designs include some form of timing device. Depending on the frequency accuracy requirements, some employ oscillators while others use off-the-shelf crystals in conjunction with the built-in oscillator circuit embedded in most microcontrollers and microprocessors. Due to their simple configuration and design, most embedded solutions use the Pierce Oscillator configuration integrated as part of the system on chip (SOC). The advantages of this solution include cost, size, and power compared to a stand-alone oscillator, while the key limitation is the proper matching of the quartz crystal with the on-board oscillator and feedback components. The figure below outlines the oscillator block and the key components that influence the overall performance of the timing loop. Cin = Inverter Capacitance Cout = Inverter Capacitance at the Input at the Output RF Quartz Crystal R Cin C1 C2 Cout s Quartz Crystal C C 1 2 Effective Loaded Capacitance as seen by the crystal = CL For example, let C1 = C2 = 27pF, Cin = 5pF, Cout = 10pF, Board Strays = 0.5pF. Therefore, specifying a crystal with 18.0 pF plating load capacitance would be the closest match for frequency accuracy. LEARN MORE AT ABRACON.COMINTRODUCTION PIERCE ANALYZER SYSTEM (PAS) ADVANCED BOARD CHARACTERIZATION SERVICE The reactive impedance (Xc) of the loop capacitors, in combination with the inverter amplifiers transconductance (gm), the current limiting resistor (Rs), and the presence or absence of an AGC circuit, determines the boundary condition of the oscillator loop design. This boundary condition, commonly referred to as the safety factor (SF), is an important parameter to ensure that the product design has sufficient margin to accommodate part-to-part and lot-to-lot variations, as well as eliminating product performance uncertainty in production volume. Historically, design engineers have optimized their circuit performance via trial and error, at the expense of significant investment in time. Further, to properly determine the oscillator loop dynamics, there is no other choice but to break the oscillator loop and make key measurements using specialized equipment such as a current probe. Lastly, these measurements become increasingly sensitive if the timing loop is driven by a tuning fork (32.768kHz) crystal. These crystals are extremely sensitive to loading effects and extreme care and accuracy is essential to determine the in-circuit behavior of these components. For instance, automotive, medical, and consumer electronics solutions typically utilize tuning fork crystals for their real-time-clocking (RTC) needs. If the selected SOC has an inadequate gain margin, there is a high probability that some percentage of these crystals will not properly start under adverse conditions, such as low operating temperature. Another example would be a ZigBee based design which has a hard boundary condition of 40 ppm relative to the carrier, for proper operation. If the oscillator loop is not optimized, most of the 40 ppm can be consumed by tolerance alone potentially causing significant yield loss or timing error in the field. In summary, a typical product launch requires a significant investment in capital and design resources. Making a very modest investment in characterizing the timing loop is a must-have to protect this investment, as well as mitigate the risk of field failures or warranty recalls. LEARN MORE AT ABRACON.COM