240Pin DDR3L 1.35V 1600 U-DIMM 2GB Based on 256Mx8 AQD-D3L2GN16-SQ1 Advantech AQD-D3L2GN16-SQ1 Datasheet Rev. 0.0 2017-07-07 1 240Pin DDR3L 1.35V 1600 U-DIMM 2GB Based on 256Mx8 AQD-D3L2GN16-SQ1 Description Pin Identification Symbol Function AQD-D3L2GN16-SQ1 is a DDR3L 1600Mbps U-DIMM high-speed, memory module that use 8pcs of 256Mx 64 A0~A14, BA0~BA2 Address/Bank input bits DDR3L SDRAM in FBGA package and a 2K bits DQ0~DQ63 Bi-direction data bus. serial EEPROM on a 240-pin printed circuit board. DQS0~DQS7 Data strobes AQD-D3L2GN16-SQ1 is a Dual In-Line Memory Module /DQS0~/DQS7 Differential Data strobes and is intended for mounting into 240-pin edge connector CK0, /CK0,CK1, /CK1 Clock Input. (Differential pair) sockets. CKE0, CKE1 Clock Enable Input. Synchronous design allows precise cycle control with the ODT0, ODT1 On-die termination control line use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, /S0, /S1 DIMM rank select lines. programmable latencies allow the same device to be /RAS Row address strobe useful for a variety of high bandwidth, high performance /CAS Column address strobe memory system applications. /WE Write Enable Features DM0~DM7 Data masks/high data strobes Lead-free and Halogen free products are RoHS VDD Core power supply Compliant JEDEC standard 1.35V(1.28V~1.45V) Power supply VDDQ I/O driver power supply Backward compatible for 1.5V(1.425V~1.575V) V DQ DQ reference supply REF VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Command/address reference MRS Cycle with address key programs V CA REF supply - CAS Latency( 5,6,7,8,9,10,11) V SPD SPD EEPROM power supply DD - Burst Length (BL):8 and 4 with Burst Chop(BC) Bi-directional, differential data strobe (DQS and /DQS) I2C serial bus address select for SA0~SA2 Differential clock input (CK, /CK) operation EEPROM 8 bit pre-fetch SCL I2C serial bus clock for EEPROM Double-data-rate architecture two data transfers per SDA I2C serial bus data for EEPROM clock cycle VSS Ground Internal calibration through ZQ pin On Die Termination with ODT pin /RESET Set DRAMs Known State Auto refresh and self refresh VTT DRAM I/O termination supply Average Refresh Period 7.8us at lower than TCASE NC No Connection 85C, 3.9us at 85C < TCASE 95C PCB Gold Plating: 30u min 2