A3959 DMOS Full-Bridge PWM Motor Driver Features and Benefits Description 3 A, 50 V Output Rating Designed for pulse width modulated (PWM) current control of Low r Outputs (270 m, Typical) DC motors, the A3959 is capable of output currents to 3 A and DS(on) Mixed, Fast, and Slow Current-Decay Modes operating voltages to 50 V. Internal fixed off-time PWM current- Synchronous Rectification for Low Power Dissipation control timing circuitry can be adjusted via control inputs to Internal UVLO and Thermal-Shutdown Circuitry operate in slow, fast, and mixed current-decay modes. Crossover-Current Protection PHASE and ENABLE input terminals are provided for use Internal Oscillator for Digital PWM Timing in controlling the speed and direction of a DC motor with externally applied PWM-control signals. Internal synchronous Packages: rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with Package B, 24-pin DIP hysteresis, undervoltage monitoring of supply and charge with exposed tabs pump, and crossover-current protection. Special power-up sequencing is not required. The A3959 provides a choice of three power packages, a 24-pin Package LB, 24-pin SOIC DIP with batwing tabs (package suffix B), a 24-lead SOIC with internally fused pins with four internally-fused pins (package suffix LB), and a thin (<1.2 mm) 28-pin TSSOP with an exposed thermal pad (suffix LP). In all cases, the power pins and tabs are at ground potential and need no electrical isolation. Each package is lead (Pb) free, with 100% matte tin leadframes. Package LP, 28-pin TSSOP with exposed thermal pad Not to scale Functional Block Diagram VBB VDD + LOGIC LOAD SUPPLY SUPPLY CHARGE PUMP VREG CHARGE UNDER- BANDGAP BANDGAP VOLTAGE & PUMP REGULATOR VDD TO VDD CREG FAULT DETECT TSD SLEEP OUTA EXT MODE CONTROL LOGIC PHASE ENABLE OUTB SENSE TO VDD CS ZERO BLANK CURRENT PWM DETECT RS PFD1 TIMER PFD2 CURRENT OSC SENSE ROSC REFERENCE BUFFER & REF w 10 VREF Dwg. FP-048-2A 29319.37L CP1 GATE DRIVE CP2 CPA3959 DMOS Full-Bridge PWM Motor Driver Selection Guide Part Number Package Packing A3959SB-T 24-pin DIP with exposed tabs 15 per tube A3959SLBTR-T 24-pin SOIC with internally fused pins 1000 per reel A3959SLPTR-T 28-pin TSSOP with exposed thermal pad 4000 per reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Load Supply Voltage V 50 V BB Logic Supply Voltage V 7.0 V DD Continuous 0.3 to V + 0.3 V DD Input Voltage V IN t < 30 ns 1.0 to V + 1.0 V w DD Continuous 0.5 V Sense Voltage V S t < 3 s 2.5 V w Reference Voltage V V V REF DD Output current rating may be limited by duty cycle, am- Repetitive 3.0 A bient temperature, and heat sinking. Under any set of Output Current I OUT conditions, do not exceed the speci ed current rating Peak, < 3 s 6.0 A or a junction temperature of 150C. Package Power Dissipation P See Thermal Characteristics D Operating Ambient Temperature T Range S 20 to 85 C A Fault conditions that produce excessive junction temperature will activate Maximum Junction Temperature T (max) the devices thermal shutdown circuitry. These conditions can be toler- 150 C J ated but should be avoided. Storage Temperature T 55 to 150 C stg Allegro MicroSystems, LLC 2 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000 www.allegromicro.com