A4950 Full-Bridge DMOS PWM Motor Driver Description Features and Benefits Low R outputs DS(on) Designed for pulse width modulated (PWM) control of DC Overcurrent protection (OCP) motors, the A4950 is capable of peak output currents to 3.5 A Motor short protection and operating voltages to 40 V. Motor lead short to ground protection Input terminals are provided for use in controlling the speed and Motor lead short to battery protection direction of a DC motor with externally applied PWM control Low Power Standby mode signals. Internal synchronous rectification control circuitry is Adjustable PWM current limit provided to lower power dissipation during PWM operation. Synchronous rectification Internal undervoltage lockout (UVLO) Internal circuit protection includes overcurrent protection, Crossover-current protection motor lead short to ground or supply, thermal shutdown with hysteresis, undervoltage monitoring of V , and crossover- BB Package: 8-pin SOICN with exposed current protection. thermal pad (suffix LJ) The A4950 is provided in a low-profile 8-pin SOICN package with exposed thermal pad (suffix LJ) that is lead (Pb) free, with 100% matte tin leadframe plating. Not to scale Functional Block Diagram Load Supply Charge OSC VBB Pump IN1 Control Logic Disable OUT1 TSD UVLO IN2 OUT2 7V GND LSS VREF 10 (Optional) A4950-DS, Rev. 1A4950 Full-Bridge DMOS PWM Motor Driver Selection Guide Part Number Packing A4950ELJTR-T 3000 pieces per 13-in. reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit Load Supply Voltage V 40 V BB Logic Input Voltage Range V 0.3 to 6 V IN V Input Voltage Range V 0.3 to 6 V REF REF Sense Voltage (LSS pin) V 0.5 to 0.5 V S Motor Outputs Voltage V 2 to 42 V OUT Output Current I Duty cycle = 100% 3.5 A OUT Transient Output Current i T < 500 ns 6 A OUT W Operating Temperature Range T Temperature Range E 40 to 85 C A Maximum Junction Temperature T (max) 150 C J Storage Temperature Range T 55 to 150 C stg Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Value Unit 2 On 2-layer PCB with 0.8 in. exposed 2-oz. copper each side 62 C/W Package Thermal Resistance R JA On 4-layer PCB based on JEDEC standard 35 C/W *Additional thermal information available on the Allegro website. Terminal List Table Number Name Function Pin-out Diagram 1 GND Ground 2 IN2 Logic input 2 GND OUT2 1 8 3 IN1 Logic input 1 IN2 2 7 LSS 4 VREF Analog input PAD IN1 3 6 OUT1 5 VBB Load supply voltage VREF 4 5 VBB 6 OUT1 DMOS full bridge output 1 7 LSS Power return sense resistor connection 8 OUT2 DMOS full bridge output 2 PAD Exposed pad for enhanced thermal dissipation Allegro MicroSystems, Inc. 2 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000 www.allegromicro.com