Rev A PC404A Evaluation Module Users Guide 1. Introduction The PC404A facilitates evaluation of the TAOS analog linear sensor arrays (TSL201, TSL202, TSL208, TSL1401, TSL1402, TSL1406, TSL1410, or TSL1301) by providing the necessary timing and clock signals to support the on-board imaging device. The designer is then free to investigate the properties and performance of the device without having to design and construct support circuitry. A single 5 volt regulated power supply (and light) are the only inputs required. An oscilloscope is required for observation and analysis of the output signals. 2. Functional Description The linear sensor array support circuitry of the PC404A consists of an oscillator, a counter/divider and logic to provide the imager with the required clock and integration pulse signals for operation. The oscillator is built around a TLC555 timer. The oscillator output is inverted and fed into divider U10 to provide lower frequency options. The clock frequency may PC404A Linear Array EVM DVdd 2MHz Clock CLK 1 DVdd DVdd R23 2MHz 1 2 U9 470 1 2 1MHz 4 U10 1 2 U12A 500KHz 4 9 U11A 2 R 7 3 1 7 2 5 DIS Q Clock Select D PR Q 3 10 CLK 6 2 3 1 THR CLK 13 R24 2 5 74HC00 11 12 6 TR CV CT=0 CL Q 14 220 1 15 C14 1 74HC74 .1 TLC555 2 74HC4040 1 2 DVdd C15 180p 1 2 128uS 2 1 2 256uS U11B U13 1 2 512uS U11C 1 2 4 1mS 10 9 1 2 6 2mS 8 10 7 1 2 5 4mS CLK 9 6 1 2 8mS Test Points 5 1 2 16mS 74HC00 3 1 2 74HC00 32mS TP10 TP11 11 2 1 2 64mS CT=0 SI 1 SO2 1 SI Integration Time SMD Bypass on Control Reverse Side DVdd SO TP12 74HC4040 CLK 1 TP13 8 Pin/16 Pin Location CLK U11D C18 C19 C20 AO1 1 C16 C17 C21 12 TP14 AO O SI 11 1 1 1 1 1 1 1 13 GND TSL1401 .1 .1 .1 .1 .1 .1 TSL213 74HC00 TP15 Linear Array Device 2 2 2 2 2 2 8 Pin 1 GND TSL1402 Jumper setting DVdd U14 DVdd DVdd W1 TP16 DVdd 1 DVdd 1 14 1 Vdd NC DVdd SI 2 13 2 W2 1 SI SO 1 8 Pin CLK 3 12 3 JP28 CLK GND 1 AO1 4 11 C27 Jumper setting Jumper AO1 NC 1 DVdd VCC 2 5 10 10 GND SI 2 2 3 SO2 6 9 2 SO 2 NC 7 8 AO1 Power Jumper Vdd AO2 1 1 1 1 1 1 DVdd R25 TSL1402 C22 C23 C24 C25 C26 330 Draftsman Tim Flanigan .1 .1 .1 .1 .1 2 2 2 2 2 2 Figure 1 - PC404A Schematic Diagram be selected from 2 MHz, 1 MHz and 500 kHz by moving the clock select jumper to the desired position (see Figure 1). U10, U11, and U12 generate the serial input (SI) pulse with the proper relationship to the clock (see Figure 2). The sensor integration time, defined by the time between SI clock pulses, may be selected from 128uS to 64mS by placing the jumper at the appropriate location. The analog output (AO) pin of the linear array is routed to the AO test terminal on the right side of the board, as are SI, clock (CLK), and serial out (SO) signals. The SO signal is generated by the linear array device (applies to TSL202, TSL208, TSL1402, TSL1406, and TSL1410 only). A supply terminal (DVdd) and 2 GND terminals are provided for applying +5 volts and common ground. Power may be applied through terminal block JP28 if desired. The analog output voltage is directly proportional to the light intensity and the integration time up to the devices saturation level (3.5V typ). The proportionality constant is the responsivity of 2 the device given in (V*cm /uW*sec). Responsivity is wavelength dependent. For the linear arrays the responsivity will peak at about 770nm. 01 2 128 129 CLK SI 12 128 AO Figure 2 - System Timing (AO output for TSL1401 shown) 3. Operation To operate the PC404A, apply 5VDC to the board using a regulated lab power supply. Connect an oscilloscope probe to the Ao terminal and the scope ground to one of the GND terminals. For best results, connect another probe to the SI terminal and use that signal to trigger the oscilloscope.