TSL1401CCS-LF ams

TSL1401CCS 128 1 Linear Sensor Array With Hold The TSL1401CCS linear sensor array consists of a 128 1 array General Description of photodiodes, associated charge amplifier circuitry, and a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 63.5m (H) by 55.5m (W) with 63.5m center-to-center spacing and 8m spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of the TSL1401CCS linear sensor array, are listed below: Figure 1: Added Value of Using TSL1401CCS Benefits Features Enables High-Resolution Edge Detection 128 1 Sensor-Element Organization Supports High Resolution OCR, Bar Code Reading 400 Dots-Per-Inch (DPI) Sensor Pitch Facilitates Grey Scale Scanning and Accurate High Linearity and Uniformity Positioning Usable Over a Wide Range of Light Levels Wide Dynamic Range... 4000:1 (72dB) Simplifies ADC Interface Output Referenced to Ground Minimal Smearing of Moving Images Low Image Lag... 0.5% Typ Allows High Scan Rate for Faster Throughput Operation to 8MHz No Special Power Supply Required Single 3V to 5V Supply Utilizes Full ADC Input Range Rail-to-Rail Output Swing Minimizes Component Count No External Load Resistor Required Available in a Solder-Bump Linear Array Small Form Factor and Footprint Package Compatible With Most Process Flows Lead (Pb) Free and RoHS Compliant ams Datasheet Page 1 v1-00 2016-Jan-18 Document FeedbackT S L1 40 1C CS Ge n e r a l De s c rip t ion Applications The TSL1401CCS is intended for use in a wide variety of applications, including: Image Scanning Mark and Code Reading Optical Character Recognition (OCR) and Contact Imaging Edge Detection and Positioning Optical Linear and Rotary Encoding Block Diagram The functional blocks of this device are shown below: Figure 2: TSL1401CCS Block Diagram 8 Pixel 1 Pixel Pixel Pixel V 1 DD Integrator 2 3 128 Analog Reset S1 Bus 2 2 Output 6 1 3 AO Buffer + S2 Sample/Hold/ Output 4, 5 GND Switch Control Logic Gain 2 Hold Trim Q1 Q2 Q3 Q128 7 SO 3 C L K 128-B it Shift Register 1 SI Page 2 ams Datasheet Document Feedback v1-00 2016-Jan-18