TSL1401CL 128 1 LINEAR SENSOR ARRAY WITH HOLD TAOS136 JULY 2011 CL PACKAGE 128 1 Sensor-Element Organization (TOP VIEW) 400 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity SI 1 8 NC Wide Dynamic Range . 4000:1 (72 dB) Output Referenced to Ground CLK 2 7 GND Low Image Lag . 0.5% Typ Operation to 8 MHz AO 3 6 GND Single 3-V to 5-V Supply Rail-to-Rail Output Swing (AO) V 4 5 NC DD No External Load Resistor Required Replacement for TSL1401RLF NC No internal connection RoHS Compliant Package Drawing is Not to Scale Description The TSL1401CL linear sensor array consists of a 128 1 array of photodiodes, associated charge amplifier circuitry, and an internal pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The array is made up of 128 pixels, each of which has a photo-sensitive area of 3,524.3 square micrometers. There is 8-m spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. Functional Block Diagram 4 Pixel 1 Pixel Pixel Pixel V DD 1 Integrator 2 3 128 Analog Reset S1 Bus 2 2 Output 3 1 3 AO Buffer + S2 Sample/Hold/ Output 6, 7 GND Switch Control Logic Gain Hold Q1 Q2 Q3 Q128 Trim 2 CLK 128-Bit Shift Register 1 SI The LUMENOLOGY Company Copyright 2011, TAOS Inc. Texas Advanced Optoelectronic Solutions Inc. 1001 Klein Road Suite 300 Plano, TX 75074 (972) 673-0759 www.taosinc.com 1TSL1401CL 128 1 LINEAR SENSOR ARRAY WITH HOLD TAOS136 JULY 2011 Terminal Functions TERMINAL DESCRIPTIONDESCRIPTION NAME NO. AO 3 Analog output. CLK 2 Clock. The clock controls charge transfer, pixel output, and reset. GND 6, 7 Ground (substrate). All voltages are referenced to the substrate. NC 5, 8 No internal connection. SI 1 Serial input. SI defines the start of the data-out sequence. V 4 Supply voltage. Supply voltage for both analog and digital circuits. DD Detailed Description The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. An internal signal, called Hold, is generated from the rising edge of SI and transmitted to analog switches in the pixel circuit. This causes all 128 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first th 18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19 clock. On the th 129 clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a th th high impedance state. Note that this 129 clock pulse is required to terminate the output of the 128 pixel, and return the internal logic to a known state. If a minimum integration time is desired, the next SI pulse may be th presented after a minimum delay of t (pixel charge transfer time) after the 129 clock pulse. qt AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With V = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V DD for saturation light level. When the device is not in the output phase, AO is in a high-impedance state. The voltage developed at analog output (AO) is given by: V = V + (R ) (E )(t ) out drk e e int where: V is the analog output voltage for white condition out V is the analog output voltage for dark condition drk 2 R is the device responsivity for a given wavelength of light given in V/(J/cm ) e 2 E is the incident irradiance in W/cm e t is integration time in seconds int A 0.1 F bypass capacitor should be connected between V and ground as close as possible to the device. DD The TSL1401CL is intended for use in a wide variety of applications, including: image scanning, mark and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical linear and rotary encoding. Copyright 2011, TAOS Inc. The LUMENOLOGY Company 2 www.taosinc.com