TSL3301CL 102 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG-TO-DIGITAL CONVERTER TAOS141 JULY 2011 CL PACKAGE 102 1 Sensor Element Organization (TOP VIEW) 300 Dots-per-Inch Pixel Pitch High Sensitivity SCLK 1 8 NC On-Chip 8-Bit Analog-to-Digital Conversion Three-Zone Programmable Offset (Dark Level) and Gain V 2 7 GND DD High Speed Serial Interface 1 MHz Pixel Rate SDIN 3 6 GND Single 3-V to 5.5-V Supply Replacement for TSL3301 SDOUT 4 5 NC RoHS Compliant NC No internal connection Package Drawing is Not to Scale Description The TSL3301CL is a high-sensitivity 300-dpi, linear optical sensor array with integrated 8-bit analog-to-digital converters. The array consists of 102 pixels: 100 inner pixels and 2 end pixels. The inner pixels measure 85 m (H) by 77 m (W) on 85-m centers and the end pixels are 132 m (H) by 49 m (W). Associated with each pixel is a charge integrator/amplifier and sample-hold circuit. All pixels have concurrent integration periods and sampling times. The array is split into three 34-pixel zones, with each zone having programmable gain and offset levels. Data communication is accomplished through a three-wire serial interface. Intended for use in high performance, cost-sensitive scanner applications, the TSL3301CL is based on a linear sensor array die that has expanded capability, including multi-die addressing and cascade options. Please contact TAOS for additional information on die and multi-die package availability. Functional Block Diagram PIXEL ARRAY WITH INTEGRATORS AND SH (51-bit shift register) PIXCLK SI HOLD ZERO LEFT ODD LEFT EVEN RIGHT ODD RIGHT EVEN IREF 8 DB<7:0> SCLK 5 ADDR<4:0> VREF OUTPUT CHARGE-TO- DIGITAL I/O SDIN READ VOLTAGE CONVERTER AND IREF WITH PROGRAMMABLE CONTROL WRITE GAINS AND OFFSETS 3 SDOUT SECTOR BIAS BLOCK RESET/SAMPLE VREF DUAL 8BIT START IREF SA ADC ADCLK The LUMENOLOGY Company Copyright 2011, TAOS Inc. Texas Advanced Optoelectronic Solutions Inc. 1001 Klein Road Suite 300 Plano, TX 75074 (972) 673-0759 www.taosinc.com 1TSL3301CL 102 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG-TO-DIGITAL CONVERTER TAOS141 JULY 2011 Terminal Functions TERMINAL I/OI/O DESCRIPTIONDESCRIPTION NAME NO. GND 6, 7 Ground SCLK 1 I System clock input for serial I/O and all internal logic. SDIN 3 I Serial data input. Data is clocked in on the rising edge of SCLK. SDOUT 4 O Serial data output. Data is clocked out on the falling edge of SCLK. V 2 Positive supply voltage. DD Detailed Description The TSL3301CL is a 102 1 linear optical array with onboard A/D conversion. It communicates over a serial digital interface and operates over a 3 V to 5.5 V range. The array is divided into three 34-pixel zones (left, center, and right), with each zone having programmable gain and offset (dark signal) correction. The sensor consists of 102 photodiodes, also called pixels, arranged in a linear array. Light energy impinging on a pixel generates a photocurrent, which is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity (E ) on that pixel and to the integration time (t ). At maximum programmed gain, one LSB corresponds to e int approximately 300 electrons. Integration, sampling, output, and reset of the integrators are performed by the control logic in response to commands input via the SDIN pin. Data is read out on the SDOUT pin. A normal sequence of operation consists of a pixel reset (RESET), start of integration (STARTInt), integration period, sampling of integrators (SAMPLEInt), and pixel output (READPixel). Reset sets all the integrators to zero. Start of integration releases the integrators from the reset state and defines the beginning of the integration period. Sampling the integrators ends the integration period and stores the charge accumulated in each pixel in a sample and hold circuit. Reading the pixels causes the sampled value of each pixel to be converted to 8-bit digital format and output on the SDOUT pin. All 102 pixels are output sequentially unless interrupted by an abort (ABORTPixel) command or reset by a RESET command. Gain adjustment is controlled by three 5-bit DACs, one for each of the the three zones. Table 1 lists the gain settings and the corresponding pixel values. Offset is affected by the gain setting and may have to be adjusted after gain changes are made. Offset correction is controlled by three 8-bit sign-magnitude DACs and is performed in the analog domain prior to the digital conversion. There is a separate offset DAC for each of the three zones. Codes 0h 7Fh correspond to positive offset values and codes 80h FFh correspond to negative offset values. The offset correction is proportional to the gain setting. At minimal gain, one LSB of the offset DAC corresponds to approximately 1/3 LSB of the device output, and at maximum gain, to about 1 LSB of the device output. Note that the gain and offset registers are in indeterminate states after power up and must be set by the controller as required. Sign-magnitude is a binary representation in which the most significant bit (MSB) is used to represent the sign of the number, with the remaining bits representing the magnitude. An MSB of 1 indicates a negative number. Copyright 2011, TAOS Inc. The LUMENOLOGY Company 2 www.taosinc.com