CMOS Dual 8-Bit a Buffered Multiplying DAC AD7528 FEATURES FUNCTIONAL BLOCK DIAGRAM On-Chip Latches for Both DACs V A REF +5 V to +15 V Operation DACs Matched to 1% R A V FB DD Four Quadrant Multiplication DB0 OUT A TTL/CMOS Compatible DATA INPUT LATCH DAC A INPUTS BUFFER Latch Free (Protection Schottkys not Required) DB7 AGND APPLICATIONS Digital Control of: AD7528 DAC A/ DAC B Gain/Attenuation R B FB CONTROL CS Filter Parameters LOGIC OUT B WR Stereo Audio Circuits LATCH DAC B X-Y Graphics DGND V B REF 1 GENERAL DESCRIPTION ORDERING GUIDE The AD7528 is a monolithic dual 8-bit digital/analog converter Temperature Relative Gain Package featuring excellent DAC-to-DAC matching. It is available in 2 3 Model Ranges Accuracy Error Options skinny 0.3 wide 20-lead DIPs and in 20-lead surface mount packages. AD7528JN 40 C to +85 C 1 LSB 4 LSB N-20 AD7528KN 40 C to +85 C 1/2 LSB 2 LSB N-20 Separate on-chip latches are provided for each DAC to allow AD7528LN 40 C to +85 C 1/2 LSB 1 LSB N-20 easy microprocessor interface. AD7528JP 40 C to +85 C 1 LSB 4 LSB P-20A Data is transferred into either of the two DAC data latches via a AD7528KP 40 C to +85 C 1/2 LSB 2 LSB P-20A AD7528LP 40 C to +85 C 1/2 LSB 1 LSB P-20A common 8-bit TTL/CMOS compatible input port. Control AD7528JR 40 C to +85 C 1 LSB 4 LSB R-20 input DAC A/DAC B determines which DAC is to be loaded. AD7528KR 40 C to +85 C 1/2 LSB 2 LSB R-20 The AD7528s load cycle is similar to the write cycle of a ran- AD7528LR 40 C to +85 C 1/2 LSB 1 LSB R-20 dom access memory and the device is bus compatible with most AD7528AQ 40 C to +85 C 1 LSB 4 LSB Q-20 8-bit microprocessors, including 6800, 8080, 8085, Z80. AD7528BQ 40 C to +85 C 1/2 LSB 2 LSB Q-20 The device operates from a +5 V to +15 V power supply, dis- AD7528CQ 40 C to +85 C 1/2 LSB 1 LSB Q-20 AD7528SQ 55 C to +125 C 1 LSB 4 LSB Q-20 sipating only 20 mW of power. AD7528TQ 55 C to +125 C 1/2 LSB 2 LSB Q-20 Both DACs offer excellent four quadrant multiplication charac- AD7528UQ 55 C to +125 C 1/2 LSB 1 LSB Q-20 teristics with a separate reference input and feedback resistor for NOTES each DAC. 1 Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts will be marked with cerdip designator Q. 2 PRODUCT HIGHLIGHTS Processing to MIL-STD-883C, Class B is available. To order, add suffix /883B to part number. For further information, see Analog Devices 1990 Military Products 1. DAC-to-DAC matching: since both of the AD7528 DACs are Databook. fabricated at the same time on the same chip, precise match- 3 N = Plastic DIP P = Plastic Leaded Chip Carrier Q = Cerdip R = SOIC. ing and tracking between DAC A and DAC B is inherent. The AD7528s matched CMOS DACs make a whole new range of applications circuits possible, particularly in the audio, graphics and process control areas. 2. Small package size: combining the inputs to the on-chip DAC latches into a common data bus and adding a DAC A/DAC B select line has allowed the AD7528 to be packaged in either a small 20-lead DIP, SOIC or PLCC. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: (V A = V B = +10 V OUT A = OUT B = O V unless otherwise noted) AD7528SPECIFICATIONS REF REF V = +5 V V = +15 V DD DD 1 Parameter Version T = +25 CT , T T = +25 CT , T Units Test Conditions/Comments A MIN MAX A MIN MAX 2 STATIC PERFORMANCE Resolution All 8 8 8 8 Bits Relative Accuracy J, A, S 1 1 1 1 LSB max This is an Endpoint Linearity Specification K, B, T 1/2 1/2 1/2 1/2 LSB max L, C, U 1/2 1/2 1/2 1/2 LSB max Differential Nonlinearity All 1 1 1 1 LSB max All Grades Guaranteed Monotonic Over Full Operating Temperature Range Gain Error J, A, S 4 6 4 5 LSB max Measured Using Internal R A and R B FB FB K, B, T 2 4 2 3 LSB max Both DAC Latches Loaded with 11111111 L, C, U 1 3 1 1 LSB max Gain Error is Adjustable Using Circuits of Figures 4 and 5 3 Gain Temperature Coefficient D Gain/D Temperature All 0.007 0.007 0.0035 0.0035 %/ C max Output Leakage Current OUT A (Pin 2) All 50 400 50 200 nA max DAC Latches Loaded with 00000000 OUT B (Pin 20) All 50 400 50 200 nA max Input Resistance (V A, V B) All 8 8 8 8 kW min Input Resistance TC = 300 ppm/ C, Typical REF REF 15 15 15 15 kW max Input Resistance is 11 kW V A/V B Input Resistance REF REF Match All 1 1 1 1% max 4 DIGITAL INPUTS Input High Voltage V All 2.4 2.4 13.5 13.5 V min IH Input Low Voltage V All 0.8 0.8 1.5 1.5 V max IL Input Current I All 1 10 1 10 m A max V = 0 or V IN IN DD Input Capacitance DB0DB7 All 10 10 10 10 pF max WR, CS, DAC A/DAC B All 15 15 15 15 pF max 3 SWITCHING CHARACTERISTICS See Timing Diagram Chip Select to Write Set Up Time All 90 100 60 80 ns min tCS Chip Select to Write Hold Time All 0 0 10 15 ns min tCH DAC Select to Write Set Up Time All 90 100 60 80 ns min tAS DAC Select to Write Hold Time All 0 0 10 15 ns min t AH Data Valid to Write Set Up Time All 80 90 30 40 ns min t DS Data Valid to Write Hold Time All 0 0 0 0 ns min t DH Write Pulsewidth t All 90 100 60 80 ns min WR POWER SUPPLY See Figure 3 I All 2 2 2 2 mA max All Digital Inputs V or V DD IL IH All 100 500 100 500 m A max All Digital Inputs 0 V or V DD (Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as 5 AC PERFORMANCE CHARACTERISTICS Output Amplifiers) V = +5 V V = +15 V DD DD 1 Parameter Version T = +25 CT , T T = +25 CT , T Units Test Conditions/Comments A MIN MAX A MIN MAX DC SUPPLY REJECTION (D GAIN/D V ) All 0.02 0.04 0.01 0.02 % per % max D V = 5% DD DD 2 CURRENT SETTLING TIME All 350 400 180 200 ns max To 1/2 LSB. OUT A/OUT B Load = 100 W . WR = CS = 0 V. DB0DB7 = 0 V to V or DD V to 0 V DD PROPAGATION DELAY (From Digital In- V A = V B = +10 V REF REF put to 90% of Final Analog Output Current) All 220 270 80 100 ns max OUT A, OUT B Load = 100 W C = 13 pF EXT WR = CS = 0 V DB0DB7 = 0 V to V or DD V to 0 V DD DIGITAL-TO-ANALOG GLITCH IMPULSE All 160 440 nV sec typ For Code Transition 00000000 to 11111111 OUTPUT CAPACITANCE C A All 50 50 50 50 pF max DAC Latches Loaded with 00000000 OUT C B 50 505050pF max OUT C A 120 120 120 120 pF max DAC Latches Loaded with 11111111 OUT C B 120 120 120 120 pF max OUT 6 AC FEEDTHROUGH V A to OUT A All 70 65 70 65 dB max V A, V B = 20 V p-p Sine Wave REF REF REF V B to OUT B 70 65 70 65 dB max 100 kHz REF 2 REV. B