CMOS 12-Bit a Buffered Multiplying DAC AD7545 FEATURES FUNCTIONAL BLOCK DIAGRAM 12-Bit Resolution R FB Low Gain TC: 2 ppm/ C typ 20 Fast TTL Compatible Data Latches AD7545 Single +5 V to +15 V Supply R Small 20-Lead 0.3 DIP and 20-Terminal Surface Mount 1 OUT 1 12-BIT Packages V 19 REF MULTIPLYING DAC 2 AGND Latch Free (Schottky Protection Diode Not Required) Low Cost 12 Ideal for Battery Operated Equipment WR 17 18 V DD INPUT DATA LATCHES CS 16 3 DGND 12 DB11DB0 (PINS 415) GENERAL DESCRIPTION The AD7545 is particularly suitable for single supply operation The AD7545 is a monolithic 12-bit CMOS multiplying DAC and applications with wide temperature variations. with onboard data latches. It is loaded by a single 12-bit wide The AD7545 can be used with any supply voltage from +5 V to word and directly interfaces to most 12- and 16-bit bus systems. +15 V. With CMOS logic levels at the inputs the device dissi- Data is loaded into the input latches under the control of the CS pates less than 0.5 mW for V = +5 V. DD and WR inputs tying these control inputs low makes the input latches transparent, allowing direct unbuffered operation of the DAC. PIN CONFIGURATIONS DIP LCCC PLCC OUT 1 1 20 R FB AGND 2 19 V REF 3 2 1 20 19 3 2 1 20 19 DGND 3 18 V DD PIN 1 DB11 (MSB) 4 18 V DD 4 18 V IDENTIFIER DB11 (MSB) DB11 (MSB) 4 17 WR DD DB10 5 17 WR DB10 5 17 WR AD7545 AD7545 DB10 5 16 CS AD7545 DB9 6 16 DB9 6 16 CS CS TOP VIEW TOP VIEW TOP VIEW DB0 (MSB) DB9 6 15 (Not to Scale) (Not to Scale) (Not to Scale) DB8 7 15 DB0 (LSB) DB8 7 15 DB0 (LSB) DB8 7 14 DB1 DB7 8 14 DB1 DB7 8 14 DB1 DB2 DB7 8 13 9 1011 1213 9 10 11 12 13 DB6 9 12 DB3 DB5 10 11 DB4 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 617/329-4700 World Wide Web Site: (V = +10 V, V = O V, AGND = DGND unless otherwise noted) AD7545SPECIFICATIONS REF OUT1 V = +5 V V = +15 V DD DD Limits Limits 1 1 Parameter Version T = + 25 CT T T = + 25 CT T Units Test Conditions/Comments A MIN, MAX A MIN, MAX STATIC PERFORMANCE Resolution All 12 12 12 12 Bits J, A, S 2 2 2 2 LSB max K, B, T 1 1 1 1 LSB max L, C, U 1/2 1/2 1/2 1/2 LSB max GL, GC, GU 1/2 1/2 1/2 1/2 LSB max Differential Nonlinearity J, A, S 4 4 4 4 LSB max 10-Bit Monotonic T to T MIN MAX K, B, T 1 1 1 1 LSB max 12-Bit Monotonic T to T MIN MAX L, C, U 1 1 1 1 LSB max 12-Bit Monotonic T to T MIN MAX GL, GC, GU 1 1 1 1 LSB max 12-Bit Monotonic T to T MIN MAX 2 Gain Error (Using Internal RFB) J, A, S 20 20 25 25 LSB max DAC Register Loaded with K, B, T 10 10 15 15 LSB max 1111 1111 1111 L, C, U 5 6 10 10 LSB max Gain Error Is Adjustable Using GL, GC, GU 1 2 6 7 LSB max the Circuits of Figures 4, 5, and 6 3 Gain Temperature Coefficient Gain/ Temperature All 5 5 10 10 ppm/C max Typical Value is 2 ppm/C for V = +5 V DD 3 DC Supply Rejection Gain/ V All 0.015 0.03 0.01 0.02 % per % max V = 5% DD DD Output Leakage Current at OUT1 J, K, L, GL 10 50 10 50 nA max DB0DB11 = 0 V WR, CS = 0 V A, B, C, GC 10 50 10 50 nA max S, T, U, GU 10 200 10 200 nA max DYNAMIC PERFORMANCE 3 Current Settling Time All 2 2 2 2 s max To 1/2 LSB. OUT1 Load = 100 . DAC Output Measured from Falling Edge of WR, CS = 0. 3 Propagation Delay (from Digital Input Change to 90% 4 of Final Analog Output) All 300 250 ns max OUT1 Load = 100 , C = 13 pF EXT Digital-to-Analog Glitch Inpulse All 400 250 nV sec typ V = AGND REF 5 AC Feedthrough At OUT1 All 5 5 5 5 mV p-p typ V = 10 V, 10 kHz Sinewave REF REFERENCE INPUT Input Resistance All 7 7 7 7 k min Input Resistance TC = 300 ppm/C typ (Pin 19 to GND) 25 25 25 25 k max Typical Input Resistance = 11 k ANALOG OUTPUT 3 Output Capacitance C All 70 70 70 70 pF max DB0DB11 = 0 V, WR, CS = 0 V OUT1 C 200 200 200 200 pF max DB0DB11 = V , WR, CS = 0 V OUT1 DD DIGITAL INPUTS Input High Voltage V All 2.4 2.4 13.5 13.5 V min IH Input Low Voltage V All 0.8 0.8 1.5 1.5 V max IL 6 Input Current I All 1 10 1 10 A max V = 0 or V IN IN DD 3 Input Capacitance DB0DB11 All 5 5 5 5 pF max V = 0 IN WR, CS All 20 20 20 20 pF max V = 0 IN 7 SWITCHING CHARACTERISTICS Chip Select to Write Setup Time All 280 380 180 200 ns min See Timing Diagram t 200 270 120 150 ns typ CS Chip Select to Write Hold Time t All 0 0 0 0 ns min CH Write Pulse Width t All 250 400 160 240 ns min t t , t 0 WR CS WR CH 175 280 100 170 ns typ Data Setup Time All 140 210 90 120 ns min t 100 150 60 80 ns typ DS Data Hold Time t All 10 10 10 10 ns min DH POWER SUPPLY I All 2 2 2 2 mA max All Digital Inputs V or V DD IL IH 100 500 100 500 A max All Digital Inputs 0 V to V DD 10 10 10 10 A typ All Digital Inputs 0 V to V DD NOTES 1 Temperature range as follows: J, K, L, GL versions, 0C to +70C A, B, C, GC versions, 25C to +85C S, T, U GU versions, 55C to +125C. 2 This includes the effect of 5 ppm max gain TC. 3 Guaranteed but not tested. 4 DB0DB11 = 0 V to V or V to 0 V. DD DD 5 Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND. 6 Logic inputs are MOS gates. Typical input current (+25C) is less than 1 nA. 7 Sample tested at +25C to ensure compliance. Specifications subject to change without notice. 2 REV. A