2 LC MOS a (8+4) Loading Dual 12-Bit DAC AD7537 FUNCTIONAL BLOCK DIAGRAM FEATURES Two 12-Bit DACs in One Package DAC Ladder Resistance Matching: 0.5% Space Saving Skinny DIP and Surface Mount Packages 4-Quadrant Multiplication Low Gain Error (1 LSB max Over Temperature) Byte Loading Structure Fast Interface Timing APPLICATIONS Automatic Test Equipment Programmable Filters Audio Applications Synchro Applications Process Control GENERAL DESCRIPTION The AD7537 contains two 12-bit current output DACs on one monolithic chip. A separate reference input is provided for each DAC. The dual DAC saves valuable board space, and the monolithic construction ensures excellent thermal tracking. Both DACs are guaranteed 12-bit monotonic over the full tem- perature range. The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure. It is designed for right-justified data format. The control signals for register loading are A0, A1, CS, WR and UPD. Data is PRODUCT HIGHLIGHTS loaded to the input registers when CS and WR are low. To 1. DAC to DAC Matching: transfer this data to the DAC registers, UPD must be taken low Since both DACs are fabricated on the same chip, precise with WR. matching and tracking is inherent. Many applications which Added features on the AD7537 include an asynchronous CLR are not practical using two discrete DACs are now possible. line which is very useful in calibration routines. When this is Typical matching: 0.5%. taken low, all registers are cleared. The double buffering of the 2. Small Package Size: data inputs allows simultaneous update of both DACs. Also, The AD7537 is packaged in small 24-pin 0.3 DIPs and in each DAC has a separate AGND line. This increases the device 28-terminal surface mount packages. versatility for instance one DAC may be operated with AGND biased while the other is connected in the standard 3. Wide Power Supply Tolerance: configuration. The device operates on a +12 V to +15 V V , with 10% DD tolerance on this nominal figure. All specifications are The AD7537 is manufactured using the Linear Compatible 2 guaranteed over this range. CMOS (LC MOS) process. It is speed compatible with most microprocessors and accepts TTL, 74HC and 5 V CMOS logic level inputs. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703(V = +12 V to +15 V, 610%, V = V = 10 V I = AGND = 0 V, DD REFA REFB OUTA AD7537SPECIFICATIONS I = AGNDB = 0 V. All specifications T to T unless otherwise noted.) OUTB MIN MAX J, A K, B L, C S T U Parameter Versions Versions Versions Version Version Version Units Test Conditions/Comments ACCURACY Resolution 12 12 12 12 12 12 Bits Relative Accuracy 1 1/2 1/2 1 1/2 1/2 LSB max Differential Nonlinearity 1 1 1 1 1 1 LSB max All grades guaranteed mono- tonic over temperature. Gain Error 6 3 1 6 3 2 LSB max Measured using R , R . FBA FBB Both DAC registers loaded with all 1s. 2 Gain Temperature Coefficient Gain/Temperature 5 5 5 5 5 5 ppm/C max Typical value is 1 ppm/C Output Leakage Current I OUTA +25C 10 10 10 10 10 10 nA max DAC A Register loaded T to T 150 150 150 250 250 250 nA max with all 0s MIN MAX I OUTB +25C 10 10 10 10 10 10 nA max DAC B Register loaded T to T 150 150 150 250 250 250 nA max with all 0s MIN MAX REFERENCE INPUT Input Resistance 999999k min Typical Input Resistance = 14 k 20 20 20 20 20 20 k max V , V REFA REFB Input Resistance Match 3 3 1 3 3 1 % max Typically 0.5% DIGITAL INPUTS V (lnput High Voltage) 2.4 2.4 2.4 2.4 2.4 2.4 V min IH V (Input Low Voltage) 0.8 0.8 0.8 0.8 0.8 0.8 V max IIL I (Input Current) IN +25C 1 1 1 1 1 1 A max V = V IN DD T to T 10 10 10 10 10 10 A max MIN MAX 2 C (lnput Capacitance) 10 10 10 10 10 10 pF max IN 3 POWER SUPPLY V 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max DD I 222222mA max DD AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance only and are not subject to test. (V = +12 V to +15 V V = V = +10 V I = AGNDA = 0 V, I = AGNDB = 0 V. Output Amplifiers are AD644 except where noted.) DD REFA REFB OUTA OUTB Parameter T = +258CT = T , T Units Test Conditions/Comments A A MIN MAX Output Current Settling Time 1.5 s max To 0.01% of full-scale range. I load = 100 , C = 13 pF. OUT EXT DAC output measured from falling edge of WR. Typical Value of Settling Time is 0.8 s. Digital-to-Analog Glitch lmpulse 7 nV-s typ Measured with V = V = 0 V. I , I load = 100 , REFA REFB OUTA OUTB C = 13 pF. DAC registers alternately loaded with all 0s and all 1s. EXT 4 AC Feedthrough V to I 70 65 dB max V , V = 20 V p-p 10 kHz sine wave. REFA OUTA REFA REFB V to I 70 65 dB max DAC registers loaded with all 0s. REFB OUTB Power Supply Rejection Gain/V 0.01 0.02 % per % max V = V max V min DD DD DD DD Output Capacitance C 70 70 pF max DAC A, DAC B loaded with all 0s OUTA C 70 70 pF max OUTB C 140 140 pF max DAC A, DAC B loaded with all 1s OUTA C 140 140 pF max OUTB Channel-to-Channel Isolation V to I 84 dB typ V = 20 V p-p 10 kHz sine wave, V = 0 V. REFA OUTB REFA REFB Both DACs loaded with all 1s. V to I 84 dB typ V = 20 V p-p 10 kHz sine wave, V = 0 V. REFB OUTA REFB REFA Both DACs loaded with all 1s. Digital Crosstalk 7 nV-s typ Measured for a Code Transition of all 0s to all 1s. I , I load = 100 , C = 13 pF. OUTA OUTB EXT Output Noise Voltage Density 25 nV/Hz typ Measured between R and I or R and I FBA OUTA FBB OUTB. (10 Hz100 kHz) Frequency of measurement is 10 Hz100 kHz. Total Harmonic Distortion 82 dB typ V = 6 V rms, 1 kHz. Both DACs loaded with all 1s. IN NOTES 1 Temperature range as follows: J, K, L Versions: 40C to +85C 2 Sample tested at +25C to ensure compliance. A, B, C Versions: 40C to +85C 3 Functional at V = 5 V, with degraded specifications. DD S, T, U Versions: 55C to +125C 4 Pin 12 (DGND) on ceramic DIPs is connected to lid. Specifications subject to change without notice. 2 REV. 0