2 LC MOS Quad 8-Bit D/A Converter AD7226 FEATURES FUNCTIONAL BLOCK DIAGRAM Four 8-Bit DACs with Output Amplifiers V V Skinny 20-Lead DIP, SOIC, SSOP, and PLCC Packages REF DD Microprocessor-Compatible TTL/CMOS-Compatible No User Trims A V A LATCH A OUT DAC A Extended Temperature Range Operation Single Supply Operation Possible D A B V B LATCH B DAC B OUT APPLICATIONS T MSB Process Control A DATA (8-BIT) Automatic Test Equipment B LSB V C C OUT Automatic Calibration of Large System Parameters, LATCH C DAC C U S e.g., Gain/Offset V D D OUT LATCH D DAC D WR CONTROL A1 AD7226 LOGIC A0 V AGND AGND SS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7226 contains four 8-bit voltage-output digital-to- 1. DAC-to-DAC Matching analog converters, with output buffer amplifiers and interface Since all four DACs are fabricated on the same chip at the logic on a single monolithic chip. No external trims are required same time, precise matching and tracking between the DACs to achieve full specified performance for the part. is inherent. Separate on-chip latches are provided for each of the four D/A 2. Single-Supply Operation converters. Data is transferred into one of these data latches The voltage mode configuration of the DACs allows the through a common 8-bit TTL/CMOS (5 V) compatible input AD7226 to be operated from a single power supply rail. port. Control inputs A0 and A1 determine which DAC is 3. Microprocessor Compatibility loaded when WR goes low. The control logic is speed-compat- The AD7226 has a common 8-bit data bus with individual ible with most 8-bit microprocessors. DAC latches, providing a versatile control architecture for Each D/A converter includes an output buffer amplifier capable simple interface to microprocessors. All latch enable signals of driving up to 5 mA of output current. The amplifiers offsets are level triggered. are laser-trimmed during manufacture, thereby eliminating any 4. Small Size requirement for offset nulling. Combining four DACs and four op amps plus interface logic Specified performance is guaranteed for input reference voltages into a 20-pin package allows a dramatic reduction in board from 2 V to 12.5 V with dual supplies. The part is also specified space requirements and offers increased reliability in systems for single supply operation at a reference of 10 V. using multiple converters. Its pinout is aimed at optimizing board layout with all the analog inputs and outputs at one The AD7226 is fabricated in an all ion-implanted high speed 2 end of the package and all the digital inputs at the other. Linear Compatible CMOS (LC MOS) process, which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip. REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 20 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies.1 (V = 11.4 V to 16.5 V, V = 5 V 10%, AGND = DGND = 0 V V = +2 V to (V 4 V) , DD SS REF DD AD7226SPECIFICATIONS unless otherwise noted. All Specifications T to T unless otherwise noted.) MIN MAX DUAL SUPPLY 2 Parameter K, B Versions Unit Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Total Unadjusted Error 1LSB max V = 15 V 5%, V = 10 V DD REF Relative Accuracy 0.5 LSB max Differential Nonlinearity 1LSB max Guaranteed Monotonic Full-Scale Error 0.5 LSB max Full-Scale Temperature Coefficient 20 ppm/C typ V = 14 V to 16.5 V, V = +10 V DD REF Zero Code Error 20 mV max Zero Code Error Temperature Coefficient 50 mV/ C typ REFERENCE INPUT Voltage Range 2 to (V 4) V min to V max DD Input Resistance 2 kW min 3 Input Capacitance 50 pF min Occurs when each DAC is loaded with all 0s. 200 pF max Occurs when each DAC is loaded with all 1s. DIGITAL INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Leakage Current 1 mA max V = 0 V or V IN DD Input Capacitance 8 pF max Input Coding Binary DYNAMIC PERFORMANCE 4 Voltage Output Slew Rate 2.5 V/ms min 4 Voltage Output Settling Time 4 ms max V = 10 V Settling Time to 1/2 LSB REF Digital Crosstalk 10 nV secs typ Minimum Load Resistance 2 kW min V = 10 V OUT POWER SUPPLIES V Range 11.4/16.5 V min/V max For Specified Performance DD I 13 mA max Outputs Unloaded V = V or V DD IN INL INH I 11 mA max Outputs Unloaded V = V or V SS IN INL INH 4, 5 SWITCHING CHARACTERISTICS Address to Write Setup Time, t 0ns min AS Address to Write Hold Time, t 0ns min AH Data Valid to Write Setup Time, t 50 ns min DS Data Valid to Write Hold Time, t 0ns min DH Write Pulsewidth, t 50 ns min WR NOTES 1 Maximum possible reference voltage. 2 Temperature ranges are as follows: K Version: 40 C to +85 C B Version: 40 C to +85 C 3 Guaranteed by design. Not production tested. 4 Sample Tested at 25 C to ensure compliance. 5 Switching Characteristics apply for single and dual supply operation. Specifications subject to change without notice. 2 REV. 4 o f 1 4