73S8014R Smart Card Interface Simplifying System Integration DATA SHEET September 2008 DESCRIPTION APPLICATIONS Set-Top-Box Conditional Access and Pay-per-View The Teridian 73S8014R is a single smart card (ICC) interface General purpose smart card readers circuit, firmware compatible with 8024-type devices for configurations where only asynchronous cards must be ADVANTAGES supported. It is derived from the 73S8024RN industry- standard electrical interface. The 73S8014R has been Same advantages as the Teridian 73S80xxR family: optimized to match most of the typical Set-Top-Box / A/V VCC card generated by an LDO regulator Conditional Access applications. Optimization essentially Very low power dissipation (saves up to 1/2W) involved a smaller pin-count, support for single I/O, and Fewer external components are required maximum card current of 65mA (ISO-7816 / EMV compliance). Better noise performance True card over-current detection The 73S8014R interfaces with the host processor through the same bus (digital I/Os) as the 73S8024RN, which is Firmware compatibility with all 8024 ICs compatible with any other 8024-type IC. As a result, the Small format 20SO package 73S8014R is a very attractive cost-reduction path from traditional 8024 ICs. The 73S8014R has been designed to FEATURES provide full electrical compliance with ISO 7816-3 and EMV 4.0 specifications. Card Interface: Complies with ISO 7816-3 and EMV 4.0 Interfacing with the system controller is done through a control bus, composed of digital inputs to control the Supports 3V / 5V cards interface, and one interrupt output to inform the system ISO 7816-3 Activation / Deactivation sequencer controller of the card presence and faults. Automated deactivation upon hardware fault (i.e. upon drop on V power supply or card overcurrent) DD The card clock can be generated by an on-chip oscillator using an external crystal or by connection to an externally The V voltage supervisor threshold value (fault) can DD supplied clock signal. be externally adjusted Over-current detection 130mA max The 73S8014R incorporates an ISO 7816-3 Card CLK clock frequency up to 20MHz activation/deactivation sequencer that controls the card signals. Level-shifters drive the card signals with the System Controller Interface: selected card voltage (3V or 5V), coming from an internal 3 Digital inputs control the card activation / Low Drop-Out (LDO) voltage regulator. This LDO regulator is deactivation, card reset and card voltage powered by a dedicated power supply input V . Digital PC 2 Digital inputs control the card clock frequency circuitry is powered separately by a digital power supply V . DD 1 Digital output, interrupt to the system controller, With its embedded LDO regulator, the 73S8024RN is a reports to the host the card presence and faults cost-effective solution for any application where a 5V Crystal oscillator or host clock, up to 27MHz (typically -5% +10%) power supply is available. Regulator Power Supply: Emergency card deactivation is initiated upon card extraction 4.75V to 5.5V or upon any fault detected by the protection circuitry. The fault can be a card over-current, VCC undervoltage or power Digital Interfacing: 2.7V to 5.5V supply fault (V ). The card over-current circuitry is a true DD 6kV ESD protection on the card interface current detection function, as opposed to V voltage drop CC Package: SO 20-pin detection, as usually implemented in non-Teridian 8024 interface ICs. RoHS compliant (6/6) lead-free package The V voltage fault has a threshold voltage that can be DD adjusted with an external resistor network. It allows automated card deactivation at a customized V voltage DD threshold value. It can be used, for instance, to match the system controller operating voltage range. Rev. 1.0 2008 Teridian Semiconductor Corporation 1 73S8014R Data Sheet DS 8014R 012 FUNCTIONAL DIAGRAM VDD VPC vdd circuits VCC FAULT INTERNAL POWER SUPPLY VDDF ADJ VDD FAULT VOLTAGE REFERENCE vref LDO bias currents VPD - internal supply REGULATOR R-C CMDVCC 1.5MHz CONTROLLER OSC. GND RSTIN AND 5V/ V REGISTERS VCC TEST FAULT LOGIC RESET RST BUFFER OFF SC CLOCK CKDIV1 CLK SEQUENCER BUFFER CKDIV2 CLOCK XTALIN XTAL CLOCK VDD CKT OSC GENERATION PRES XTALOUT vdd circuits I/O IOUC SMART CARD I/O BUFFER vcc circuits GND Figure 1: 73S8014R Block Diagram 2 Rev. 1.0