Stereo, 24-Bit, 192 kHz, Multibit, Sigma-Delta DAC AD1852 FEATURES APPLICATIONS 5 V stereo audio DAC system High end Accepts 16-bit/18-bit/20-bit/24-bit data DVDs, CDs, home theater systems, automotive, audio Supports 24 bits, 192 kHz sample rate systems, sampling musical keyboards, digital mixing Accepts a wide range of sample rates including consoles, and digital audio effects processors 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz GENERAL DESCRIPTION Multibit - modulator with perfect differential linearity The AD1852 is a complete, high performance, single-chip, stereo restoration for reduced idle tones and noise floor digital, audio playback system. It is comprised of a multibit, - Data-directed scrambling DACleast sensitive to jitter modulator, digital interpolation filters, and analog output drive Differential output for optimum performance circuitry. Other features include an on-chip, stereo attenuator 117 dB signal-to-noise (not muted) at 48 kHz sample rate and mute, programmed through an SPI-compatible serial control (A-weighted mono) port. The AD1852 is fully compatible with all known DVD 114 dB signal-to-noise (not muted) at 48 kHz sample rate formats, including 192 kHz, as well as 96 kHz sample frequencies (A-weighted stereo) and 24 bits. It is also backwards compatible by supporting 117 dB dynamic range (not muted) at 48 kHz sample rate 50 s/15 s digital de-emphasis intended for Red Book compact (A-weighted mono) discs, as well as de-emphasis at 32 kHz and 48 kHz sample rate. 114 dB dynamic range (not muted) at 48 kHz sample rate (A-weighted stereo) The AD1852 has a very simple, but very flexible, serial data input 105 dB THD+N (mono application circuit) port that allows for glueless interconnection to a variety of ADCs, 102 dB THD+N (stereo) DSP chips, AES/EBU receivers, and sample rate converters. The 115 dB stop-band attenuation 2 AD1852 can be configured in left-justified, I S, right-justified, On-chip clickless volume control or DSP serial port compatible modes. It can support 16, 18, 20, Hardware and software controllable clickless mute and 24 bits in all modes. The AD1852 accepts serial audio data Serial (SPI) control for: serial mode, number of bits, sample in MSB first, twos-complement format. The AD1852 operates rate, volume, mute, de-emp from a single 5 V power supply. It is fabricated on a single, Digital de-emphasis processing for 32 kHz, 44.1 kHz, 48 kHz monolithic integrated circuit and is housed in a 28-lead SSOP sample rates for operation over the 0C to 70C temperature range. Clock autodivide circuit supports five master-clock frequencies Flexible serial data port with right-justified, left-justified, 2 I S-compatible and DSP serial port modes 28-Lead SSOP plastic package FUNCTIONAL BLOCK DIAGRAM DIGITAL CLOCK CONTROL DATA SUPPLY IN INPUT VOLUME MUTE 2 3 SERIAL CONTROL VOLTAGE AUTO-CLOCK AD1852 INTERFACE REFERENCE DIVIDE CIRCUIT 16-/18-/20-/24-BIT 8 f ATTEN/ MULTIBIT SIGMA- S DIGITAL DAC MUTE INTERPOLATOR DELTA MODULATOR SERIAL DATA INPUT ANALOG DATA OUTPUTS INTERFACE 2 8 f SERIAL ATTEN/ MULTIBIT SIGMA- S DAC MODE MUTE INTERPOLATOR DELTA MODULATOR 2 2 RESET MUTE DE-EMPHASIS ANALOG ZERO SUPPLY FLAG Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20002009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08457-001AD1852 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................9 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 12 General Description ......................................................................... 1 Serial Data Input Port ................................................................ 12 Functional Block Diagram .............................................................. 1 Serial Data Input Mode ............................................................. 12 Revision History ............................................................................... 2 Master Clock Autodivide Feature ............................................ 13 Specif icat ions ..................................................................................... 3 SPI Register Definitions ............................................................ 13 Analog Performance .................................................................... 3 Register Addresses ...................................................................... 14 Digital I/O (0C to 70C) ............................................................. 4 Volume Left and Volume Right Registers ............................... 14 Temperature Range ...................................................................... 4 SPI Timing................................................................................... 14 Power .............................................................................................. 4 Mute ............................................................................................. 14 Digital Filter Characteristics ....................................................... 4 Control Register ......................................................................... 15 Group Delay .................................................................................. 4 De-Emphasis ............................................................................... 15 Digital Timing ............................................................................... 5 Output Impedance ..................................................................... 15 Absolute Maximum Ratings ............................................................ 6 Reset ............................................................................................. 15 Thermal Resistance ...................................................................... 6 Control Signals ........................................................................... 15 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 18 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 18 REVISION HISTORY 11/09Rev. 0 to Rev. A Changes to Format ............................................................. Universal Changes to Note 1 ............................................................................. 1 Changes to Table 2 ............................................................................ 3 Changes to Table 11 .......................................................................... 7 Changes to Register Addresses Section and Mute Section ....... 14 Changes to Figure 29 ...................................................................... 16 1/00Revision 0: Initial Version Rev. A Page 2 of 20