SigmaDSP Multichannel 28-Bit Audio Processor AD1940/AD1941 FEATURES APPLICATIONS 16-channel digital audio processor Automotive sound systems Accepts sample rates up to 192 kHz Digital televisions 28-bit 28-bit multiplier with full 56-bit accumulator Home theater systems (Dolby digital/DTS postprocessor) Fully programmable program RAM for custom Multichannel audio systems program download Mini-component stereos Parameter RAM allows complete control of 1,024 parameters Multimedia audio Control port features safeload for transparent parameter Digital speaker crossover updates and complete mode and memory transfer control Musical instruments Target/slew RAM for click-free volume control and dynamic In-seat sound systems (aircrafts/motor coaches) parameter updates FUNCTIONAL BLOCK DIAGRAM Double precision mode for full 56-bit processing PLL for generating MCLK from 64 fS, 256 fS, 384 fS, or 4 512 fS clocks Hardware-accelerated DSP core AD1940/AD1941 21 kB (6,144 words) data memory for up to 128 ms of audio VOLTAGE REGULATOR delay at fs = 48 kHz 2 Flexible serial data port with I S-compatible, left-justified, 2 and right-justified serial port modes 28 28 2 SERIAL DATA/ DSP CORE TDM INPUTS 8- and 16-channel TDM input/output modes 2 On-chip voltage regulator for compatibility with 3.3 V and DATA FORMAT: SERIAL 5 V systems DATA/ 5.23 (SINGLE MASTER TDM PRECISION) PLL Programmable low power mode CLOCK OUTPUTS INPUT 10.46 (DOUBLE Fast start-up and boot time from power-on or reset PRECISION) 48-lead LQFP plastic package SERIAL 4 2 CONTROL SPI/I C I/O RAM ROM INTERFACE Figure 1. GENERAL DESCRIPTION The AD1940/AD1941 are a complete 28-bit, single-chip, multi- The AD1940/AD1941 are a fully programmable DSP. Easy to use software allows the user to graphically configure a custom channel audio SigmaDSP for equalization, multiband dynamic signal processing flow using blocks such as biquad filters, dyna- processing, delay compensation, speaker compensation, and mics processors, and surround sound processors. An extensive image enhancement. These algorithms can be used to compen- control port allows click-free parameter updates, along with sate for the real world limitations of speakers, amplifiers, and readback capability from any point in the algorithm flow. listening environments, resulting in a dramatic improvement of perceived audio quality. The AD1940/AD1941s digital input and output ports allow a glueless connection to ADCs and DACs by multiple, 2-channel The signal processing used in the AD1940/AD1941 is serial data streams or TDM data streams. When in TDM mode, comparable to that found in high end studio equipment. Most the AD1940/AD1941 can input 8 or 16 channels of serial data, of the processing is done in full, 56-bit double-precision mode, and can output 8 or 16 channels of serial data. The input and resulting in very good, low level signal performance and the output port configurations can be individually set. The AD1940 absence of limit cycles or idle tones. The dynamics processor is controlled by a 4-wire SPI port the AD1941 is controlled by uses a sophisticated, multiple-breakpoint algorithm often found 2 in high end broadcast compressors. a 2-wire I C bus. Other than the control interface, the functions of the two parts are identical. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. 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All rights reserved. 04607-0-001AD1940/AD1941 TABLE OF CONTENTS 2 Specifications ..................................................................................... 3 AD1941 I C Port ......................................................................... 15 Digital I/O ..................................................................................... 3 RAMs and Registers ....................................................................... 19 Power .............................................................................................. 3 Control Port Addressing ........................................................... 19 Digital Timing ............................................................................... 4 Parameter RAM Contents ......................................................... 19 PLL ................................................................................................. 5 Recommended Program/Parameter Loading Procedures .... 20 Regulator ........................................................................................ 5 Target/Slew RAM ....................................................................... 20 Temperature Range ...................................................................... 5 Safeload Registers ....................................................................... 23 Absolute Maximum Ratings ............................................................ 6 Data Capture Registers .............................................................. 23 ESD Caution .................................................................................. 6 DSP Core Control Register ....................................................... 24 Digital Timing Diagrams ................................................................. 7 RAM Configuration Register ................................................... 25 Pin Configuration and Function Descriptions ............................. 9 Control Port Read/Write Data Formats .................................. 25 Features ............................................................................................ 11 Serial Data Input/Output Ports .................................................... 28 Pin Functions .............................................................................. 12 Serial Output Control Registers ............................................... 30 Signal Processing ............................................................................ 14 Serial Input Control Register .................................................... 30 Overview ...................................................................................... 14 Initialization .................................................................................... 33 Numeric Formats ........................................................................ 14 Power-Up Sequence ................................................................... 33 Programming .............................................................................. 14 Setting Master Clock/PLL Mode .............................................. 33 Control Port ..................................................................................... 15 Voltage Regulator ....................................................................... 33 Overview ...................................................................................... 15 Outline Dimensions ....................................................................... 35 AD1940 SPI Port ........................................................................ 15 Ordering Guide .......................................................................... 35 REVISION HISTORY 4/10Rev. A to Rev. B Changes to Voltage Regulator Section ..................................... 34 Updated Outline Dimensions ................................................... 35 Changes to Ordering Guide ...................................................... 35 4/05Rev. 0 to Rev. A Added AD1941 .............................................................. Universal Changes to Specifications ............................................................ 3 Changes to Pin Function Descriptions ...................................... 9 Changes to Features Section...................................................... 11 Changes to Pin Functions Section ............................................ 13 Addition of AD1940 SPI Port Section ..................................... 15 Added Table 13 to Table 16 ....................................................... 18 7/04Revision 0: Initial Version Rev. B Page 2 of 36