THREE- STATE THREE- STATE THREE- STATE a High Speed, Logic Isolator AD261 FEATURES FUNCTIONAL BLOCK DIAGRAM Isolation Test Voltage: To 3.5 kV rms Five Isolated Logic Lines: Available in Six I/O Configurations Logic Signal Bandwidth: 20 MHz (min) LATCH F0 D LINE 0 CMV Transient Immunity: 10 kV/ms min S0 E Waveform Edge Transmission Symmetry: 61 ns LATCH Field and System Output Enable/Three-State Functions F1 D LINE 1 2 S1 E Performance Rated Over 258C to +858C UL1950, IEC950, EN60950 Certification (VDE, CE, Pending) LATCH F2 D LINE 2 S2 3 E APPLICATIONS LATCH PLC/DCS Analog Input and Output Cards F3 D 4 S3 LINE 3 Communications Bus Isolation E General Data Acquisition Applications LATCH D F4 S4 LINE 4 5 IGBT Motor Drive Controls E High Speed Digital I/O Ports 17 6 ENABLE ENABLE SYS FLD +5V dc +5V dc +5V dc 16 7 +5V dc GENERAL DESCRIPTION FLD SYS The AD261 is designed to isolate five digital control signals 5Vdc RTN 5Vdc RTN 15 8 5V RTN 5V RTN FLD SYS to/from a microcontroller and its related field I/O components. Six models allow all I/O combinations from five input lines to FIELD SYSTEM five output lines, including combinations in between. Every TYPICAL MODEL AD261 effectively replaces up to five opto-isolators. (AD261-2) Each line of the AD261 has a bandwidth of 20 MHz (min) with a propagation delay of only 14 ns, which allows for extremely PRODUCT HIGHLIGHTS fast data transmission. Output waveform symmetry is maintained Six Isolated Logic Line I/O Configurations Available: The to within 1 ns of the input so the AD261 can be used to accu- AD261 is available in six pin-compatible versions of I/O con- rately isolate time-based PWM signals. figurations to meet a wide variety of requirements. All field or system output pins of the AD261 can be set to a high Wide Bandwidth with Minimal Edge Error: The AD261 resistance three-state level by use of the two enable pins. A field affords extremely fast isolation of logic signals due to its 20 MHz output three-stated offers a convenient method of presetting bandwidth and 14 ns propagation delay. It maintains a wave- logic levels at power-up by use of pull-up/down resistors. Sys- form input-to-output edge transition error of typically less than tem side outputs being three-stated allows for easy multiplexing 1 ns (total) for positive vs. negative transition. of multiple AD261s. 3.5 kV rms Test Voltage Isolation Rating: The AD261 The isolation barrier of the AD261 B Grade is 100% tested B Grade is rated to operate at 1.25 kV rms and is 100% pro- as high as 3.5 kV rms (system to field). The barrier design also duction tested at 3.5 kV rms, using a standard ADI test method. provides excellent common-mode transient immunity from High Transient Immunity: The AD261 rejects common- 10 kV/s common-mode voltage excursions of field side termi- mode transients slewing at up to 10 kV/s without false trigger- nals relative to the system side, with no false output triggering ing or damage to the device. on either side. Each output is updated within nanoseconds by input logic tran- (Continued on page 5) sitions, the AD261 also has a continuous output update feature that automatically updates each output based on the dc level of the input. This guarantees the output is always valid 10 s after a fault condition or after the power-up reset interval. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: (Typical at T = +258C, +5 V dc , +5 V dc , t = 50 ns max unless otherwise noted) AD261SPECIFICATIONS A SYS FLD RR Parameter Conditions Min Typ Max Units INPUT CHARACTERISTICS Threshold Voltage Positive Transition (V ) +5 V dc = 4.5 V 2.0 2.7 3.15 V T+ SYS +5 V dc = 5.5 V 3.0 3.2 4.2 V SYS Negative Transition (V ) +5 V dc = 4.5 V 0.9 1.8 2.2 V T SYS +5 V dc = 5.5 V 1.2 2.2 3.0 V SYS Hysteresis Voltage (V ) +5 V dc = 4.5 V 0.4 0.9 1.4 V H SYS +5 V dc = 5.5 V 0.5 1.0 1.5 V SYS Input Capacitance (C ) 5pF IN Input Bias Current (I ) Per Input 0.5 A IN OUTPUT CHARACTERISTICS 1 Output Voltage High Level (V ) +5 V dc = 4.5 V, I = 0.02 mA 4.4 V OH SYS O +5 V dc = 4.5 V, I = 4 mA 3.7 V SYS O ) +5 V dc = 4.5 V, I = 0.02 mA 0.1 V Low Level (V OL SYS O +5 V dc = 4.5 V, I = 4 mA 0.4 V SYS O Output Three-State Leakage Current ENABLE Logic Low/High Level Respectively 0.5 A SYS/FLD 1 DYNAMIC RESPONSE (Refer to Figure 2) Max Logic Signal Frequency (f ) 50% Duty Cycle, +5 V dc = 5 V 20 MHz MIN SYS Waveform Edge Symmetry Error (t )t vs. t 1ns ERROR PHL PLH Logic Edge Propagation Delay (t , t)1425ns PHL PLH Minimum Pulsewidth (t ) 25 ns PWMIN Max Output Update Delay on Fault or After 2 Power-Up Reset Interval ( 30 s) 12 s 3 ISOLATION BARRIER RATING Operating Isolation Voltage (V ) AD261A 375 V rms CMV AD261B 1250 V rms 4 Isolation Rating Test Voltage (V ) AD261A 1750 V rms CMV TEST AD261B 3500 V rms Transient Immunity (V ) 10,000 V/s TRANSIENT Isolation Mode Capacitance (C ) Total Capacitance, All Lines 9 15 pF ISO Capacitive Leakage Current (I ) 240 V rms 60 Hz 2 A rms LEAD POWER SUPPLY Supply Voltage (+5 V dc and +5 V dc ) Rated Performance 4.5 5.5 V dc SYS FLD Operating 4.0 5.75 V dc Power Dissipation Capacitance Effective, per Input, Either Side 8 pF Effective per Output, Either SideNo Load 28 pF Quiescent Supply Current Each, +5 V dc 4mA SYS & FLD Supply Current All Lines 10 MHz (Sum of +5 V dc)18 mA SYS & FLD TEMPERATURE RANGE 5 Rated Performance (T ) 25 +85 C A Storage (T ) 40 +85 C STG NOTES 1 For best performance, bypass +5 V dc supplies to com., at or near the device (0.01 F). +5 V dc supplies are also internally bypassed with 0.05 F. 2 As the supply voltage is applied to either side of the AD261, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30 s after the point where +5 V dc passes above 3.3 V. SYS & FLD 3 Operating isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be hi-pot tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the same as a hi-pot test (but nondestructive). 4 Partial Discharge at 80 pC THLD. 5 Supply Current will increase slightly, but otherwise the unit will function within specification to 40C. Specifications are subject to change without notice. REV. 0 2