Fully Accurate, 12-/14-/16-Bit, Dual, V OUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP Data Sheet AD5025/AD5045/AD5065 ence buffer is provided on chip. The AD5025/AD5045/AD5065 FEATURES incorporate a power-on reset circuit that ensures the DAC output Low power dual 12-/14-/16-bit DAC, 1 LSB INL powers up zero scale or midscale and remains there until a valid Individual voltage reference pins write takes place to the device. The AD5025/AD5045/AD5065 Rail-to-rail operation contain a power-down feature that reduces the current consump- 4.5 V to 5.5 V power supply tion of the device to typically 400 nA at 5 V and provides software Power-on reset to zero scale or midscale selectable output loads while in power-down mode. The parts are Power down to 400 nA 5 V put into power-down mode over the serial interface. Total unad- 3 power-down functions justed error for the parts is <2.5 mV. The parts exhibit very low Per channel power-down glitch on power-up. The outputs of all DACs can be updated Low glitch upon power-up LDAC simultaneously using the function, with the added Hardware power-down lockout capability functionality of user-selectable DAC channels to simultaneously Hardware LDAC with software LDAC override function CLR update. There is also an asynchronous that clears all DACs CLR function to programmable code to a software-selectable code0 V, midscale, or full scale. The SDO daisy-chaining option 14-lead TSSOP parts also feature a power-down lockout pin, PDL, which can be used to prevent the DAC from entering power-down under any APPLICATIONS circumstances over the serial interface. Process controls PRODUCT HIGHLIGHTS Data acquisition systems Portable battery-powered instruments 1. Dual channel available in a 14-lead TSSOP package with Digital gain and offset adjustment individual voltage reference pins. Programmable voltage and current sources 2. 12-/14-/16-bit accurate, 1 LSB INL. Programmable attenuators 3. Low glitch on power-up. 4. High speed serial interface with clock speeds up to 50 MHz. GENERAL DESCRIPTION 5. Three power-down modes available to the user. The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit 6. Reset to known output voltage (zero scale or midscale). buffered voltage output nanoDAC DACs offering relative accuracy 7. Power-down lockout capability. specifications of 1 LSB INL with individual reference pins, and Table 1. Related Devices can operate from a single 4.5 V to 5.5 V supply. The AD5025/ Part No. Description AD5045/AD5065 also offer a differential accuracy specification of AD5666 Quad,16-bit buffered DAC, 16 LSB INL, TSSOP 1 LSB. The parts use a versatile 3-wire, low power Schmitt AD5024/AD5044/AD5064 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP trigger serial interface that operates at clock rates up to 50 MHz AD5062/AD5063 16-bit nanoDAC, 1 LSB INL, MSOP and is compatible with standard SPI, QSPI, MICROWIRE, AD5061 16-bit nanoDAC, 4 LSB INL, SOT-23 and DSP interface standards. The reference for the AD5025/ AD5040/AD5060 14-/16-bit nanoDAC, 1 LSB INL, SOT-23 AD5045/AD5065 are supplied from an external pin and a refer- FUNCTIONAL BLOCK DIAGRAM V V A V B POR DD REF REF LDAC BUFFER INPUT DAC SCLK DAC A V A OUT REGISTER REGISTER SYNC INTERFACE LOGIC DIN BUFFER INPUT DAC DAC B V B OUT REGISTER REGISTER LDAC POWER-DOWN SDO LOGIC AD5025/AD5045/AD5065 PDL CLR GND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 06844-001AD5025/AD5045/AD5065 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Register .............................................................................. 17 Applications ....................................................................................... 1 Standalone Mode ........................................................................ 19 General Description ......................................................................... 1 SYNC Interrupt .......................................................................... 19 Product Highlights ........................................................................... 1 Daisy-Chaining ........................................................................... 19 Functional Block Diagram .............................................................. 1 Power-On Reset and Software Reset ....................................... 20 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 20 Specifications ..................................................................................... 3 Clear Code Register ................................................................... 21 AC Characteristics ........................................................................ 4 LDAC Function ........................................................................... 21 Timing Characteristics ................................................................ 5 Power-Down Lockout ................................................................ 22 Absolute Maximum Ratings ............................................................ 7 Power Supply Bypassing and Grounding ................................ 22 ESD Caution .................................................................................. 7 Microprocessor Interfacing ....................................................... 23 Pin Configuration and Function Descriptions ............................. 8 Applications Information .............................................................. 24 Typical Performance Characteristics ............................................. 9 Using a Reference as a Power Supply for the AD5025/AD5045/AD5065 ....................................................... 24 Terminology .................................................................................... 15 Bipolar Operation Using the AD5025/AD5045/AD5065 ..... 24 Theory of Operation ...................................................................... 17 Using the AD5025/AD5045/AD5065 with a Digital-to-Analog Converter .................................................... 17 Galvanically Isolated Interface ................................................. 24 DAC Architecture ....................................................................... 17 Outline Dimensions ....................................................................... 25 Reference Buffer ......................................................................... 17 Ordering Guide .......................................................................... 25 Output Amplifier ........................................................................ 17 Serial Interface ............................................................................ 17 REVISION HISTORY 8/2016Rev. 0 to Rev. A Change to Minimum SYNC High Times (Single Channel Update) Parameter and Minimum High Time (All SYNC Channel Update) Parameter, Table 4 ............................................. 5 10/2008Revision 0: Initial Version Rev. A Page 2 of 25