Fully Accurate 14-/16-Bit V nanoDAC OUT SPI Interface 2.7 V to 5.5 V, in an SOT-23 AD5040/AD5060 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 14-/16-bit DAC, 1 LSB INL V V REF DD Power-on reset to midscale or zero scale Guaranteed monotonic by design POWER-ON AD5040/ BUF RESET AD5060 3 power-down functions OUTPUT BUFFER Low power serial interface with Schmitt-triggered inputs REF(+) DAC Small 8-lead SOT-23 package, low power V REGISTER DAC OUT Fast settling time of 4 s typically 2.7 V to 5.5 V power supply AGND Low glitch on power-up INPUT POWER-DOWN CONTROL RESISTOR CONTROL LOGIC SYNC interrupt facility LOGIC NETWORK APPLICATIONS Process control SYNC SCLK DIN DACGND Data acquisition systems Portable battery-powered instruments Figure 1. Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1. Available in a small, 8-lead SOT-23 package. The AD5040 and the AD5060, members of the ADI nanoDAC family, are low power, single 14-/16-bit buffered voltage-out 2. 14-/16-bit accurate, 1 LSB INL. DACs that operate from a single 2.7 V to 5.5 V supply. The 3. Low glitch on power-up. AD5040/AD5060 parts offer a relative accuracy specification 4. High speed serial interface with clock speeds up to 30 MHz. of 1 LSB and operation are guaranteed monotonic with a 1 LSB DNL specification. The parts use a versatile 3-wire serial 5. Three power-down modes available to the user. interface that operates at clock rates up to 30 MHz and is 6. Reset to known output voltage (midscale, zero scale). compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. The reference for both the AD5040 Table 1. Related Devices and AD5060 is supplied from an external VREF pin. A reference Part No. Description buffer is also provided on-chip. The AD5060 incorporates a AD5061 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 4 LSB INL, SOT-23 power-on reset circuit that ensures the DAC output powers up AD5062 2.7 V to 5.5 V, 16-bit nanoDAC D/A,1 LSB INL, SOT-23 to midscale or zero scale and remains there until a valid write AD5063 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 1 LSB INL, MSOP takes place to the device. The AD5040 and the AD5060 both contain a power-down feature that reduces the current con- sumption of the device to typically 330 nA at 5 V and provides software-selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface. Total unadjusted error for the parts is <2 mV. Both parts exhibit very low glitch on power-up. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2005-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04767-001AD5040/AD5060 TABLE OF CONTENTS Features .............................................................................................. 1 Reference Buffer ......................................................................... 15 Applications ....................................................................................... 1 Serial Interface ............................................................................ 15 General Description ......................................................................... 1 Power-On reset ........................................................................... 16 Functional Block Diagram .............................................................. 1 Software Reset ............................................................................. 16 Product Highlights ........................................................................... 1 Power-Down Modes .................................................................. 17 Revision History ............................................................................... 2 Microprocessor Interfacing ....................................................... 17 Specif icat ions ..................................................................................... 3 Applicat ions ..................................................................................... 19 Timing Characteristics ..................................................................... 5 Choosing a Reference for the AD5040/ AD5060 ................... 19 Absolute Maximum Ratings ............................................................ 6 Bipolar Operation Using the AD5040/ AD5060 .................... 19 ESD Caution .................................................................................. 6 Using the AD5040/AD5060 with a Galvanically Isolated Interface Chip ............................................................................. 20 Pin Configuration and Function Descriptions ............................. 7 Power Supply Bypassing and Grounding ................................ 20 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 21 Terminology .................................................................................... 14 Ordering Guide .......................................................................... 21 Theory of Operation ...................................................................... 15 DAC Architecture ....................................................................... 15 REVISION HISTORY 1/10Rev. 0 to Rev. A Changes to Table 2, Relative Accuracy (INL) and Endnote 1 .... 3 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 10/05Revision 0: Initial Version Rev. A Page 2 of 24