Fully Accurate, 16-Bit, Unbuffered V , Quad SPI OUT Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP AD5066 Total unadjusted error for the part is <0.8 mV. Zero code error FEATURES for the part is 0.05 mV typically. Low power quad 16-bit nanoDAC, 1 LSB INL Low total unadjusted error of 0.1 mV typically The AD5066 contains a power-down feature that reduces the Low zero code error of 0.05 mV typically current consumption of the device to typically 400 nA at 5 V Individually buffered reference pins and provides software selectable output loads while in power- 2.7 V to 5.5 V power supply down mode. Specified over full code range of 0 to 65535 The outputs of all DACs can be updated simultaneously using Power-on reset to zero scale or midscale the hardware LDAC function, with the added functionality of Per channel power-down with 3 power-down functions user software selectable DAC channels to update simultaneously. Hardware LDAC with software LDAC override function CLR There is also an asynchronous that clears all DACs to a CLR function to programmable code software-selectable code0 V, midscale, or full scale. Small 16-lead TSSOP PRODUCT HIGHLIGHTS APPLICATIONS 1. Quad channel available in 16-lead TSSOP, 1 LSB INL. Process control 2. Individually buffered voltage reference pins. Data acquisition systems 3. TUE = 0.8 mV max and zero code error = 0.1 mV max. Portable battery-powered instruments 4. High speed serial interface with clock speeds up to 50 MHz. Digital gain and offset adjustment 5. Three power-down modes available to the user. Programmable voltage and current sources 6. Reset to known output voltage (zero scale or midscale). GENERAL DESCRIPTION Table 1. Related Devices The AD5066 is a low power, 16-bit quad-channel, unbuffered Part No. Description voltage output nanoDAC offering relative accuracy specifica- AD5666 Quad,16-bit buffered DAC,16 LSB INL, TSSOP tions of 1 LSB INL with individual reference pins and can 1 Dual,12-/14-/16-bit buffered nanoDAC, AD5025/AD5045/AD5065 operate from a single 2.7 V to 5.5 V supply. The AD5066 also TSSOP 1 offers a differential accuracy specification of 1 LSB DNL. Quad 16-bit nanoDAC, TSSOP AD5024/AD5044/AD5064 1 Reference buffers are also provided on-chip. The part uses a AD5062 Single, 16-bit nanoDAC, SOT-23 1 versatile 3-wire, low power Schmitt trigger serial interface that AD5063 Single, 16-bit nanoDAC, MSOP AD5061 Single,16-bit nanoDAC, 4 LSB INL, SOT-23 operates at clock rates up to 50 MHz and is compatible with 1 AD5040/AD5060 14-/16-bit nanoDAC, SOT-23 standard SPI, QSPI, MICROWIRE, and most DSP interface standards. The AD5066 incorporates a power-on reset circuit 1 1 LSB INL that ensures the DAC output powers up to zero scale or midscale and remains there until a valid write to the device takes place. FUNCTIONAL BLOCK DIAGRAM V V A V B REF REF DD AD5066 LDAC INPUT DAC V A DAC A OUT REGISTER REGISTER SCLK INPUT DAC V B DAC B OUT REGISTER REGISTER INTERFACE INPUT DAC V C DAC C SYNC OUT LOGIC REGISTER REGISTER INPUT DAC V D DAC D OUT REGISTER REGISTER DIN POWER-DOWN LOGIC POWER-ON RESET POR V C V D GND LDAC REF REF CLR Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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All rights reserved. 06845-001AD5066 TABLE OF CONTENTS Features .............................................................................................. 1 DAC Architecture....................................................................... 15 Applications ....................................................................................... 1 Reference Buffer ......................................................................... 15 General Description ......................................................................... 1 Serial Interface ............................................................................ 15 Product Highlights ........................................................................... 1 Input Shift Register .................................................................... 15 Functional Block Diagram .............................................................. 1 Power-On Reset .......................................................................... 17 Revision History ............................................................................... 2 Clear Code Register ................................................................... 18 Specifications ..................................................................................... 3 LDAC Function ........................................................................... 18 AC Characteristics ........................................................................ 4 Power Supply Bypassing and Grounding ................................ 19 Timing Characteristics ................................................................ 5 Microprocessor Interfacing ....................................................... 19 Absolute Maximum Ratings ............................................................ 6 Applications Information .............................................................. 21 ESD Caution .................................................................................. 6 Using a Reference as a Power Supply ....................................... 21 Pin Configuration and Function Descriptions ............................. 7 Bipolar Operation....................................................................... 21 Typical Performance Characteristics ............................................. 8 Using the AD5066 with a Galvanically Isolated Interface .... 21 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 22 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 22 Digital-to-Analog Converter .................................................... 15 REVISION HISTORY 8/10Rev. 0 to Rev. A Change to Minimum SYNC High Time, Single Channel Update Parameter, Table 4 ............................................... 5 7/09Revision 0: Initial Version Rev. A Page 2 of 24