A W B 2 Single Channel, 128-/256-Position, I C/SPI, Nonvolatile Digital Potentiometer Data Sheet AD5121/AD5141 FEATURES FUNCTIONAL BLOCK DIAGRAM V V LOGIC DD INDEP 10 k and 100 k resistance options Resistor tolerance: 8% maximum AD5121/ Wiper current: 6 mA POWER-ON AD5141 RESET Low temperature coefficient: 35 ppm/C Wide bandwidth: 3 MHz RDAC Fast start-up time < 75 s RESET INPUT Linear gain setting mode DIS REGISTER Single- and dual-supply operation SCLK/SCL 7/8 SERIAL Independent logic supply: 1.8 V to 5.5 V INTERFACE SDI/SDA Wide operating temperature: 40C to +125C EEPROM MEMORY SYNC/ADDR0 3 mm 3 mm LFCSP Qualified for automotive applications SDO/ADDR1 GND V APPLICATIONS WP SS Figure 1. Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power supplies GENERAL DESCRIPTION The AD5121/AD5141 potentiometers provide a nonvolatile The AD5121/AD5141 are available in a compact, 16-lead, 3 mm solution for 128-/256-position adjustment applications, offering 3 mm LFCSP. The devices are guaranteed to operate over the guaranteed low resistor tolerance errors of 8% and up to 6 mA extended industrial temperature range of 40C to +125C. current density in the A, B, and W pins. Table 1. Family Models The low resistor tolerance and low nominal temperature coefficient Model Channel Position Interface Package simplify open-loop applications as well as applications requiring 1 2 AD5123 Quad 128 I C LFCSP tolerance matching. 2 AD5124 Quad 128 SPI/I C LFCSP The linear gain setting mode allows independent programming AD5124 Quad 128 SPI TSSOP 1 2 of the resistance between the digital potentiometer terminals, AD5143 Quad 256 I C LFCSP 2 through R and R string resistors, allowing very accurate AD5144 Quad 256 SPI/I C LFCSP AW WB resistor matching. AD5144 Quad 256 SPI TSSOP 2 AD5144A Quad 256 I C TSSOP The high bandwidth and low total harmonic distortion (THD) AD5122 Dual 128 SPI LFCSP/TSSOP ensure optimal performance for ac signals, making it suitable 2 AD5122A Dual 128 I C LFCSP/TSSOP for filter design. AD5142 Dual 256 SPI LFCSP/TSSOP The low wiper resistance of only 40 at the ends of the resistor 2 AD5142A Dual 256 I C LFCSP/TSSOP array allows for pin-to-pin connection. 2 AD5121 Single 128 SPI/I C LFCSP 2 2 The wiper values can be set through an SPI-/I C-compatible digital AD5141 Single 256 SPI/I C LFCSP interface that is also used to read back the wiper register and 1 Two potentiometers and two rheostats. EEPROM contents. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 10940-001AD5121/AD5141 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Data Digital Interface Selection, DIS ............................ 20 Applications ....................................................................................... 1 SPI Serial Data Interface ............................................................ 20 2 Functional Block Diagram .............................................................. 1 I C Serial Data Interface ............................................................ 22 2 General Description ......................................................................... 1 I C Address .................................................................................. 22 Revision History ............................................................................... 2 Advanced Control Modes ......................................................... 23 Specifications ..................................................................................... 3 EEPROM or RDAC Register Protection ................................. 24 Electrical CharacteristicsAD5121 .......................................... 3 LRDAC Load RDAC Input Register ( ) ..................................... 24 Electrical CharacteristicsAD5141 .......................................... 6 INDEP Pin ................................................................................... 24 Interface Timing Specifications .................................................. 9 RDAC Architecture .................................................................... 27 Shift Register and Timing Diagrams ....................................... 10 Programming the Variable Resistor ......................................... 27 Absolute Maximum Ratings .......................................................... 12 Programming the Potentiometer Divider ............................... 28 Thermal Resistance .................................................................... 12 Terminal Voltage Operating Range ......................................... 29 ESD Caution ................................................................................ 12 Power-Up Sequence ................................................................... 29 Pin Configuration and Function Descriptions ........................... 13 Layout and Power Supply Biasing ............................................ 29 Typical Performance Characteristics ........................................... 14 Outline Dimensions ....................................................................... 30 Test Circuits ..................................................................................... 19 Ordering Guide .......................................................................... 30 Theory of Operation ...................................................................... 20 Automotive Products ................................................................. 30 RDAC Register and EEPROM .................................................. 20 Input Shift Register..................................................................... 20 REVISION HISTORY 5/2017Rev. B to Rev. C Changes to Figure 7 ........................................................................ 13 Changes to Figure 7 and Table 9 ................................................... 13 Changes to Figure 16 ...................................................................... 15 Changes to Figure 16 and Figure 17 ............................................. 15 Added Figure 17 Renumbered Sequentially .............................. 15 Updated Outline Dimensions ....................................................... 30 Changes to Figure 20 ...................................................................... 16 Changes to Ordering Guide .......................................................... 30 Change to Linear Gain Setting Mode Section ............................ 23 Change to Automotive Products Section .................................... 30 Changes to RDAC Architecture Section ..................................... 27 Changes to Ordering Guide .......................................................... 30 3/2016Rev. A to Rev. B Added Automotive Products Section .......................................... 30 Changes to Features Section............................................................ 1 Changes to Logic Supply Current Parameter, Table 2 ................. 4 12/2012Rev. 0 to Rev. A Added Note 12, Table 2 .................................................................... 5 Changes to Table 10 ....................................................................... 22 Changes to Logic Supply Current Parameter, Table 3 ................. 7 Added Note 12, Table 3 .................................................................... 8 10/2012Revision 0: Initial Version Rev. C Page 2 of 32