256-Position and 33-Position a Digital Potentiometers AD5200/AD5201 FUNCTIONAL BLOCK DIAGRAM FEATURES AD5200256-Position AD5200/AD5201 AD520133-Position V V DD SS 10 k , 50 k A 3-Wire SPI-Compatible Serial Data Input CS W Single Supply 2.7 V to 5.5 V or CLK SER B Dual Supply 2.7 V for AC or Bipolar Operations REG 8/6 RDAC SDI Internal Power-On Midscale Preset REG Dx APPLICATIONS SHDN GND Mechanical Potentiometer Replacement PWR-ON PRESET Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching GENERAL DESCRIPTION has a nominal temperature coefficient of 500 ppm/C. The VR The AD5200 and AD5201 are programmable resistor devices, has a VR latch that holds its programmed resistance value. The with 256 positions and 33 positions respectively, that can be digi- VR latch is updated from an SPI-compatible serial-to-parallel tally controlled through a 3-wire SPI serial interface. The terms shift register that is loaded from a standard 3-wire serial-input programmable resistor, variable resistor (VR), and RDAC are digital interface. Eight data bits for the AD5200 and six data commonly used interchangeably to refer to digital potentiometers. bits for the AD5201 make up the data word that is clocked into These devices perform the same electronic adjustment function the serial input register. The internal preset forces the wiper to as a potentiometer or variable resistor. Both AD5200/AD5201 the midscale position by loading 80 and 10 into AD5200 and H H contain a single variable resistor in the compact MSOP AD5201 VR latches respectively. The SHDN pin forces the package. Each device contains a fixed wiper resistance at the resistor to an end-to-end open-circuit condition on the A terminal wiper contact that taps the programmable resistance at a point and shorts the wiper to the B terminal, achieving a microwatt determined by a digital code. The code is loaded in the serial power shutdown state. When SHDN is returned to logic high, input register. The resistance between the wiper and either end the previous latch setting puts the wiper in the same resistance point of the programmable resistor varies linearly with respect to setting prior to shutdown. The digital interface is still active dur- the digital code transferred into the VR latch. Each variable ing shutdown so that code changes can be made that will produce resistor offers a completely programmable value of resistance, a new wiper position when the device is returned from shutdown. between the A terminal and the wiper, or the B terminal and the All parts are guaranteed to operate over the extended industrial wiper. The fixed A-to-B terminal resistance of 10 k or 50 k temperature range of 40C to +85C. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise 781/461-3113 2012 under any patent or patent rights of Analog Devices. Fax: Analog Devices, Inc., AD5200/AD5201SPECIFICATIONS (V = 5 V 10%, or 3 V 10%, V = 0 V, V = +V , V = 0 V, DD SS A DD B 40 C < T < +85 C unless otherwise noted.) AD5200 ELECTRICAL CHARACTERISTICS A 1 Parameter Symbol Conditions Min Typ Max Unit DC CHARACTERISTICS RHEOSTAT MODE 2 Resistor Differential Nonlinearity R-DNL R , V = No Connect 1 0.25 +1 LSB WB A 2 Resistor Integral Nonlinearity R-INL R , V = No Connect 2 0.5 +2 LSB WB A 3 Nominal Resistor Tolerance R T = 25C 30 +30 % AB A Resistance Temperature Coefficient R /TV = V , Wiper = No Connect 500 ppm/C AB AB DD Wiper Resistance R V = 5 V 50 100 W DD DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution N 8 Bits 4 Differential Nonlinearity DNL 1 1/4 +1 LSB 4 Integral Nonlinearity INL 2 1/2 +2 LSB Voltage Divider Temperature Coefficient V / T Code = 80 5 ppm/C W H Full-Scale Error V Code = FF 1.5 0.5 0 LSB WFSE H Zero-Scale Error V Code = 00 0 +0.5 +1.5 LSB WZSE H RESISTOR TERMINALS 5 Voltage Range V V V V A, B, W SS DD 6 Capacitance A, B C f = 1 MHz, Measured to GND, Code = 80 45 pF A, B H 6 WC f = 1 MHz, Measured to GND, Code = 80 60 pF Capacitance W H 7 Shutdown Supply Current I V = 5.5 V 0.01 5 A DD SD DD Common-Mode Leakage I V = V = V /2 1 nA CM A B DD DIGITAL INPUTS AND OUTPUTS Input Logic High V 2.4 V IH Input Logic Low V 0.8 V IL Input Logic High V V = 3 V, V = 0 V 2.1 V IH DD SS Input Logic Low V V = 3 V, V = 0 V 0.6 V IL DD SS Input Current I V = 0 V or 5 V 1 A IL IN 6 Input Capacitance C 5pF IL POWER SUPPLIES Logic Supply V 2.7 5.5 V LOGIC Power Single-Supply Range V V = 0 V 0.3 5.5 V DD RANGE SS Power Dual-Supply Range V 2.3 2.7 V DD/SS RANGE Positive Supply Current I V = +5 V or V = 0 V 15 40 A DD IH IL Negative Supply Current I V = 5 V 15 40 A SS SS 8 Power Dissipation P V = +5 V or V = 0 V, V = +5 V, V = 0 V 0.2 mW DISS IH IL DD SS Power Supply Sensitivity PSS V = +5 V 10%, Code = Midscale 0.01 0.001 +0.01 %/% DD 6, 9 DYNAMIC CHARACTERISTICS Bandwidth 3 dB BW 10 k R = 10 k , Code = 80 600 kHz AB H BW 50 k R = 50 k , Code = 80 100 kHz AB H Total Harmonic Distortion THD V = 1 V rms, V = 0 V, f = 1 kHz, R = 10 k 0.003 % W A B AB Settling Time (10 k /50 k)t V = 5 V, V = 0 V, 1 LSB Error Band 2/9 s V W S A B Resistor Noise Voltage Density e R = 5 k , RS = 0 9 nVHz N WB WB NOTES 1 Typicals represent average readings at 25C and V = 5 V, V = 0 V. DD SS 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I = V /R for both V = +2.7 V, W DD DD V = 2.7 V. SS 3 V = V , Wiper (V ) = No connect. AB DD W 4 INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V = V and V = 0 V. DNL W A DD B specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions. 5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. A terminal is open-circuited in shutdown mode. 8 P is calculated from (I V ). CMOS logic level inputs result in minimum power dissipation. DISS DD DD 9 All dynamic characteristics use V = 5 V, V = 0 V. DD SS Specifications subject to change without notice. REV. D 2