4-Channel, 64-Position a Digital Potentiometer AD5203 FEATURES FUNCTIONAL BLOCK DIAGRAM 64 Position Replaces Four Potentiometers DAC 1 10 kV, 100 kV A1 6-BIT AD5203 6 W1 Power ShutdownLess than 5 mA LATCH V DD B1 3-Wire SPI-Compatible Serial Data Input AGND1 CK RS SHDN DGND 10 MHz Update Data Loading Rate 1 +2.7 V to +5.5 V Single Supply Operation 2 DAC 2 DAC Midscale Preset A2 SELECT 6-BIT 6 3 W2 LATCH APPLICATIONS B2 4 AGND2 CK RS Mechanical Potentiometer Replacement SHDN A1, A0 Programmable Filters, Delays, Time Constants 2 Volume Control, Panning DAC 3 8-BIT A3 Line Impedance Matching SERIAL 6-BIT 6 6 W3 LATCH LATCH Power Supply Adjustment B3 SDI D AGND3 CK RS SHDN CK Q RS GENERAL DESCRIPTION CLK DAC 4 CS A4 The AD5203 provides a quad channel, 64-position digitally- 6-BIT 6 W4 LATCH controlled variable resistor (VR) device. These parts perform the B4 AGND4 same electronic adjustment function as a potentiometer or vari- CK RS SHDN able resistor. The AD5203 contains four independent variable resistors in a 24-lead SOIC and the compact TSSOP-24 pack- ages. Each part contains a fixed resistor with a wiper contact SDO RS SHDN that taps the fixed resistor value at a point determined by a digi- tal code loaded into the controlling serial input register. The The reset RS pin forces the wiper to the midscale position by resistance between the wiper and either endpoint of the fixed loading 20 into the VR latch. The SHDN pin forces the resis- H resistor varies linearly with respect to the digital code transferred tor to an end-to-end open circuit condition on terminal A and into the VR latch. Each variable resistor offers a completely shorts the wiper to terminal B, achieving a microwatt power programmable value of resistance, between the A terminal and shutdown state. When shutdown is returned to logic-high the the wiper or the B terminal and the wiper. The fixed A-to-B previous latch settings put the wiper in the same resistance set- terminal resistance of 10 kW , or 100 kW has a 1% channel-to- ting prior to shutdown. channel matching tolerance with a nominal temperature coeffi- The AD5203 is available in a narrow body P-DIP-24, the cient of 700 ppm/ C. 24-lead surface mount package, and the compact 1.1 mm thin Each VR has its own VR latch which holds its programmed TSSOP-24 package. All parts are guaranteed to operate over the resistance value. These VR latches are updated from an internal extended industrial temperature range of 40 C to +85 C. serial-to-parallel shift register that is loaded from a standard For pin compatible higher resolution applications, see the 256- 3-wire serial-input digital interface. Eight data bits make up the position AD8403 product. data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last 6-bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy- chaining in multiple VR applications without additional external decoding logic. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: AD5203SPECIFICATIONS (V = +3 V 6 10% or +5 V 6 10%, V = +V , V = 0 V, 408C < T < +858C unless DD A DD B A ELECTRICAL CHARACTERISTICS otherwise noted) 1 Parameter Symbol Conditions Min Typ Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs 2 Resistor Differential NL R-DNL R , V = No Connect 0.25 0.1 +0.25 LSB WB A 2 Resistor Nonlinearity Error R-INL R , V = No Connect 0.5 0.1 +0.5 LSB WB A 3 Nominal Resistor Tolerance D R 30 +30 % AB Resistance Temperature Coefficient D R /DTV = V , Wiper = No Connect 700 ppm/ C AB AB DD Wiper Resistance R I = 1 V/R 45 100 W W W AB Nominal Resistance Match D R/R CH 1 to CH 2, V = V , T = +25 C 0.2 1 % O AB DD A DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N 6 Bits 4 Differential Nonlinearity Error DNL 0.25 0.1 +0.25 LSB 4 Integral Nonlinearity Error INL 0.75 0.1 +0.75 LSB Voltage Divider Temperature Coefficient D V /D T Code = 20 20 ppm/ C W H Full-Scale Error V Code = 3F 0.75 0.2 0 LSB WFSE H Zero-Scale Error V Code = 00 0 +0.1 +0.75 LSB WZSE H RESISTOR TERMINALS 5 Voltage Range V V V 0V V A, B, W DD 6 Ax, Bx C C f = 1 MHz, Measured to GND, Code = 20 75 pF Capacitance A, B H 6 Wx C f = 1 MHz, Measured to GND, Code = 20 120 pF Capacitance W H 7 I V = V , V = 0 V, SHDN = 0 0.01 5 m A Shutdown Supply Current A SD A DD B Shutdown Wiper Resistance R V = V , V = 0 V, SHDN = 0, V = +5 V 45 100 W W SD A DD B DD DIGITAL INPUTS AND OUTPUTS Input Logic High V V = +5 V 2.4 V IH DD Input Logic Low V V = +5 V 0.8 V IL DD Input Logic High V V = +3 V 2.1 V IH DD Input Logic Low V V = +3 V 0.6 V IL DD Output Logic High V R = 2.2 kW to V V 0.1 V OH L DD DD Output Logic Low V I = 1.6 mA, V = +5 V 0.4 V OL OL DD Input Current I V = 0 V or +5 V, V = +5 V 1 m A IL IN DD 6 Input Capacitance C 5pF IL POWER SUPPLIES Power Supply Range V Range 2.7 5.5 V DD Supply Current (CMOS) I V = V or V = 0 V 0.01 5 m A DD IH DD IL 8 Supply Current (TTL) I V = 2.4 V or V = 0.8 V, V = +5.5 V 0.9 4 mA DD IH IL DD 9 Power Dissipation (CMOS) P V = V or V = 0 V, V = +5.5 V 27.5 m W DISS IH DD IL DD Power Supply Sensitivity PSS D V = +5 V 10% 0.0002 0.001 %/% DD PSS D V = +3 V 10% 0.006 0.03 %/% DD 6, 10 DYNAMIC CHARACTERISTICS Bandwidth 3 dB BW 10K R = 10 kW 600 kHz AB = 100 kW 71 kHz BW 100K R AB V =1 V rms + 2 V dc, V = 2 V dc, f = 1 kHz 0.003 % Total Harmonic Distortion THD W A B Settling Time t 10K V = V , V = 0 V, 1 LSB Error Band 2 m s V W S A DD B 100K V = V , V = 0 V, 1 LSB Error Band 18 m s t S A DD B R = 5 kW , f = 1 kHz, RS = 0 9 nV/ Hz Resistor Noise Voltage e NWB WB = 50 kW , f = 1 kHz, RS = 0 29 nV/ Hz R WB 11 Crosstalk C V = V , V = 0 V 65 dB T A DD B 6, 12 INTERFACE TIMING CHARACTERISTICS Applies to All Parts Input Clock Pulsewidth t , t Clock Level High or Low 10 ns CH CL Data Setup Time t 5ns DS Data Hold Time t 5ns DH 13 CLK to SDO Propagation Delay t R = 2.2 kW , C < 20 pF 1 25 ns PD L L CS Setup Time t 10 ns CSS CS High Pulsewidth t 10 ns CSW Reset Pulsewidth t 50 ns RS CLK Fall to CS Rise Hold Time t 0ns CSH CS Rise to Clock Rise Setup t 10 ns CS1 2 REV. 0