1024-/256-Position, 1% Resistor Tolerance Error, SPI Interface and 50-TP Memory Digital Rheostat Data Sheet AD5270/AD5271 FEATURES FUNCTIONAL BLOCK DIAGRAM V DD Single-channel, 1024-/256-position resolution 20 k, 50 k, 100 k nominal resistance Maximum 1% nominal resistor tolerance error POWER-ON RESET 50-times programmable (50-TP) wiper memory AD5270/AD5271 Rheostat mode temperature coefficient: 5 ppm/C 2.7 V to 5.5 V single-supply operation RDAC 2.5 V to 2.75 V dual-supply operation for ac or bipolar SCLK REGISTER A 10/8 operations SERIAL SYNC INTERFACE SPI-compatible interface W Wiper setting readback 50-TP DIN MEMORY Power on refreshed from 50-TP memory BLOCK SDO Thin LFCSP, 10-lead, 3 mm 3 mm 0.8 mm package Compact MSOP, 10-lead, 3 mm 4.9 mm 1.1 mm package APPLICATIONS V EXT CAP GND SS Figure 1. Mechanical rheostat replacements Op-amp: variable gain control Instrumentation: gain, offset adjustment Programmable voltage to current conversions Programmable filters, delays, time constants Programmable power supply Sensor calibration The AD5270/AD5271 device wiper settings are controllable GENERAL DESCRIPTION through the SPI digital interface. Unlimited adjustments are 1 The AD5270/AD5271 are single-channel, 1024-/256-position allowed before programming the resistance value into the digital rheostats that combine industry leading variable resistor 50-TP memory. The AD5270/AD5271 do not require any performance with nonvolatile memory (NVM) in a compact external voltage supply to facilitate fuse blow and there are package. 50 opportunities for permanent programming. During 50-TP The AD5270/AD5271 ensure less than 1% end-to-end resistor activation, a permanent blow fuse command freezes the resistance tolerance error and offer 50-times programmable (50-TP) memory. position (analogous to placing epoxy on a mechanical trimmer). The guaranteed industry leading low resistor tolerance error The AD5270/AD5271 are available in a 3 mm 3 mm, 10-lead feature simplifies open-loop applications as well as precision LFCSP package and in a 10-lead MSOP package. The parts are calibration and tolerance matching applications. guaranteed to operate over the extended industrial temperature range of 40C to +125C. 1 Protected by U.S.Patent Number 7688240 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 08077-001AD5270/AD5271 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Shift Register ............................................................................... 18 Applications ....................................................................................... 1 RDAC Register ............................................................................ 18 Functional Block Diagram .............................................................. 1 50-TP Memory Block ................................................................ 18 General Description ......................................................................... 1 Write Protection ......................................................................... 18 Revision History ............................................................................... 2 RDAC and 50-TP Read Operation .......................................... 19 Specifications ..................................................................................... 3 Shut-Down Mode ....................................................................... 20 Electrical CharacteristicsAD5270 .......................................... 3 Resistor Performance Mode ...................................................... 20 Electrical CharacteristicsAD5271 .......................................... 5 Reset ............................................................................................. 20 Interface Timing Specifications .................................................. 7 SDO Pin and Daisy-Chain Operation ..................................... 21 Absolute Maximum Ratings ............................................................ 9 RDAC Architecture .................................................................... 21 Thermal Resistance ...................................................................... 9 Programming the Variable Resistor ......................................... 22 ESD Caution .................................................................................. 9 EXT CAP Capacitor .................................................................. 22 Pin Configuration and Function Descriptions ........................... 10 Terminal Voltage Operating Range ......................................... 22 Typical Performance Characteristics ........................................... 11 Power-Up Sequence ................................................................... 22 Test Circuits ..................................................................................... 17 Outline Dimensions ....................................................................... 23 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 24 Serial Data Interface ................................................................... 18 REVISION HISTORY 3/13Rev. E to Rev. F Added LFCSP Throughout .............................................................. 1 Changed Resistor Noise Density, RAW = 20 k from 50 nV/Hz Changed OTP to 50-TP Throughout.............................................. 1 to 13 nV/Hz Table 1 ...................................................................... 4 Changes to Product Title, Features, and General Description .... 1 Changed Resistor Noise Density, RAW = 20 k from 50 nV/Hz Changes to Table 1 ............................................................................. 3 to 13 nV/Hz Table 4 ...................................................................... 6 Added Table 3 Renumbered Sequentially ..................................... 4 Updated Outline Dimensions ....................................................... 23 Changes to Table 4 ............................................................................. 5 Added Table 6 ....................................................................................6 Changes to Table 8 and Table 9........................................................ 9 12/10Rev. D to Rev. E Added Figure 6 and changes to Table 10 ..................................... 10 Changes to SDO Pin Description ................................................. 10 Replaced Typical Performance Characteristics Section ............ 11 Changes to SDO Pin and Daisy-Chain Operation Section ....... 21 Changes to Figure 44 ...................................................................... 21 Updated Outline Dimensions ....................................................... 23 11/10Rev. C to Rev. D Changes to Ordering Guide .......................................................... 24 Changes to Figure 25 ...................................................................... 14 3/10Rev. 0 to Rev. A 9/10Rev. B to Rev. C Changes to Product Title and General Description.....................1 Changes to Figure 3 Caption ........................................................... 7 Changes to Figure 4 Caption ........................................................... 8 Changes to Theory of Operation Section...................................14 Deleted Daisy-Chain Operation Section, Added SDO Pin and 10/09Revision 0: Initial Version Daisy-Chain Operation Section ................................................... 21 5/10Rev. A to Rev. B Rev. F Page 2 of 24