2.7 V to 5.5 V, 140 A, Rail-to-Rail Output 8-Bit DAC in a SOT-23 AD5300 FEATURES FUNCTIONAL BLOCK DIAGRAM V Single 8-Bit DAC DD GND 6-Lead SOT-23 and 8-Lead MSOP Packages POWER-ON AD5300 Micropower Operation: 140 A 5 V RESET Power-Down to 200 nA 5 V, 50 nA 3 V REF (+) REF () DAC OUTPUT 2.7 V to 5.5 V Power Supply 8-BIT V OUT REGISTER BUFFER DAC Guaranteed Monotonic by Design Reference Derived from Power Supply Power-On Reset to 0 V INPUT POWER-DOWN CONTROL 3 Power-Down Functions CONTROL LOGIC RESISTOR LOGIC NETWORK Low Power Serial Interface with Schmitt-Triggered Inputs On-Chip Output Buffer Amplifier, Rail-to-Rail Operation SYNC Interrupt Facility SYNC SCLK DIN Qualified for automotive applications APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5300 is a single, 8-bit buffered voltage output DAC that 1. Available in 6-lead SOT-23 and 8-lead MSOP packages. operates from a single 2.7 V to 5.5 V supply, consuming 115 A 2. Low power, single-supply operation. This part operates from a at 3 V. Its on-chip precision output amplifier allows rail-to-rail single 2.7 V to 5.5 V supply and typically consumes 0.35 mW output swing to be achieved. The AD5300 uses a versatile 3-wire at 3 V and 0.7 mW at 5 V, making it ideal for battery-powered serial interface that operates at clock rates up to 30 MHz and is applications. compatible with standard SPI, QSPI, MICROWIRE, and 3. The on-chip output buffer amplifier allows the output of DSP interface standards. the DAC to swing rail-to-rail with a slew rate of 1 V/s. 4. Reference derived from the power supply. 1 The reference for the AD5300 is derived from the power supply 5. High speed serial interface with clock speeds up to 30 MHz. inputs and thus gives the widest dynamic output range. The part Designed for very low power consumption. The interface incorporates a power-on reset circuit that ensures that the DAC powers up only during a write cycle. output powers up to 0 V and remains there until a valid write takes 6. Power-down capability. When powered down, the DAC place to the device. The part contains a power-down feature that typically consumes 50 nA at 3 V and 200 nA at 5 V. reduces the current consumption of the device to 200 nA at 5 V and provides software selectable output loads while in power- down mode. The part is put into power-down mode over the serial interface. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 0.7 mW at 5 V, reducing to 1 W in power-down mode. The AD5300 is one of a family of pin-compatible DACs. The AD5310 is the 10-bit version, and the AD5320 is the 12-bit version. The AD5300/AD5310/AD5320 are available in 6-lead SOT-23 packages and 8-lead MSOP packages. 1 Patent pending protected by U.S. Patent No. 5684481. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20032010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 00471-001(V = 2.7 V to 5.5 V R = 2 k to GND C = 500 pF to GND all specifications DD L L T to T , unless otherwise noted.) AD5300SPECIFICATIONS MIN MAX 1 B Version Parameter Min Typ Max Unit Conditions/Comments 2 STATIC PERFORMANCE Resolution 8 Bits Relative Accuracy 1 LSB See Figure 2. Differential Nonlinearity 0.25 LSB Guaranteed Monotonic by Design. See Figure 3. Zero-Code Error +0.5 +3.5 LSB All Zeros Loaded to DAC Register. See Figure 6. Full-Scale Error 0.5 3.5 LSB All Ones Loaded to DAC Register. See Figure 6. Gain Error 1.25 % of FSR Zero-Code Error Drift 20 V/C Gain Temperature Coefficient 5 ppm of FSR/C 3 OUTPUT CHARACTERISTICS Output Voltage Range 0 V V DD Output Voltage Settling Time 4 6 s 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex). R = 2 k 0 pF < C < 500 pF. See Figure 16. L L Slew Rate 1 V/s Capacitive Load Stability 470 pF R = . L 1000 pF R = 2 k . L Digital-to-Analog Glitch Impulse 20 nV-s 1 LSB Change Around Major Carry. See Figure 19. Digital Feedthrough 0.5 nV-s DC Output Impedance 1 Short-Circuit Current 50 mA V = 5 V. DD 20 mA V = 3 V. DD Power-Up Time 2.5 s Coming Out of Power-Down Mode. V = 5 V. DD 5 s Coming Out of Power-Down Mode. V = 3 V. DD 3 LOGIC INPUTS Input Current 1 A V , Input Low Voltage 0.8 V V = 5 V. INL DD V , Input Low Voltage 0.6 V V = 3 V. INL DD V , Input High Voltage 2.4 V V = 5 V. INH DD V , Input High Voltage 2.1 V V = 3 V. INH DD Pin Capacitance 3 pF POWER REQUIREMENTS V 2.7 5.5 V DD I (Normal Mode) DAC Active and Excluding Load Current. DD V = 4.5 V to 5.5 V 140 250 AV = V and V = GND. DD IH DD IL V = 2.7 V to 3.6 V 115 200 AV = V and V = GND. DD IH DD IL I (All Power-Down Modes) DD V = 4.5 V to 5.5 V 0.2 1 AV = V and V = GND. DD IH DD IL V = 2.7 V to 3.6 V 0.05 1 AV = V and V = GND. DD IH DD IL POWER EFFICIENCY I /I 93 % I = 2 mA. V = 5 V. OUT DD LOAD DD NOTES 1 Temperature range as follows: B Version: 40C to +105C. 2 Linearity calculated using a reduced code range of 4 to 251. Output unloaded. 3 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. REV. D 2