2.5 V to 5.5 V, 120 A, 2-Wire Interface,
Voltage-Output 8-/10-/12-Bit DACs
Data Sheet
AD5301/AD5311/AD5321
FEATURES GENERAL DESCRIPTION
1
AD5301: buffered voltage output 8-bit DAC The AD5301/AD5311/AD5321 are single 8-/10-/12-bit, buff-
AD5311: buffered voltage output 10-bit DAC
ered, voltage-output DACs that operate from a single 2.5 V to
AD5321: buffered voltage output 12-bit DAC
5.5 V supply, consuming 120 A at 3 V. The on-chip output
6-lead SOT-23 and 8-lead MSOP packages
amplifier allows rail-to-rail output swing with a slew rate of
2
Micropower operation: 120 A at 3 V
0.7 V/s. It uses a 2-wire (I C-compatible) serial interface that
2
2-wire (I C-compatible) serial interface
operates at clock rates up to 400 kHz. Multiple devices can share
Data readback capability
the same bus.
2.5 V to 5.5 V power supply
The reference for the DAC is derived from the power supply
Guaranteed monotonic by design over all codes
inputs and thus gives the widest dynamic output range. These
Power-down to 50 nA at 3 V
devices incorporate a power-on reset circuit, which ensures that
Reference derived from power supply
the DAC output powers up to 0 V and remains there until a
Power-on reset to 0 V
valid write takes place. The devices contain a power-down
On-chip rail-to-rail output buffer amplifier
feature that reduces the current consumption of the device to
3 power-down functions
50 nA at 3 V and provides software-selectable output loads
while in power-down mode.
APPLICATIONS
Portable battery-powered instruments The low power consumption in normal operation makes these
Digital gain and offset adjustment DACs ideally suited to portable battery-operated equipment. The
Programmable voltage and current sources
power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,
Programmable attenuators
reducing to 1 W in all power-down modes.
FUNCTIONAL BLOCK DIAGRAM
V
DD
AD5301/AD5311/AD5321
SCL
REF
SDA
DAC
8-/10-/12-BIT
BUFFER V
INTERFACE
OUT
REGISTER
DAC
LOGIC
A0
A1*
POWER-DOWN
LOGIC
RESISTOR
NETWORK
POWER-ON
RESET
GND PD*
*AVAILABLE ON 8-LEAD VERSION ONLY
Figure 1.
1
Protected by U.S. Patent No. 5684481.
Rev. C Document Feedback
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00927-001AD5301/AD5311/AD5321 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Output Amplifier ........................................................................ 13
Applications ....................................................................................... 1 Power-On Reset .......................................................................... 13
General Description ......................................................................... 1 Serial Interface ................................................................................ 14
Functional Block Diagram .............................................................. 1 2-Wire Serial Bus ........................................................................ 14
Revision History ............................................................................... 2 Input Shift Register .................................................................... 14
Specifications ..................................................................................... 3 Write Operation.......................................................................... 15
AC Characteristics ........................................................................ 5 Read Operation........................................................................... 16
Timing Characteristics ................................................................ 5 Power-Down Modes .................................................................. 17
Absolute Maximum Ratings ............................................................ 6 Applications Notes ......................................................................... 18
ESD Caution .................................................................................. 6 Using the REF193/REF195 as a Power Supply ........................ 18
Pin Configurations and Function Descriptions ........................... 7 Bipolar Operation Using the AD5301/ AD5311/AD5321 .... 18
Terminology ...................................................................................... 8 Multiple Devices on One Bus ................................................... 18
Typical Performance Characteristics ............................................. 9 CMOS Driven SCL and SDA Lines.......................................... 18
Theory of Operation ...................................................................... 13 Power Supply Decoupling ......................................................... 19
Digital-to-Analog ....................................................................... 13 Outline Dimensions ....................................................................... 20
Resistor String ............................................................................. 13 Ordering Guide .......................................................................... 21
REVISION HISTORY
6/2016Rev. B to Rev. C
Changes to Figure 33 and Figure 34 ............................................. 16
Changes to Ordering Guide .......................................................... 22
3/2007Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Table 4 ............................................................................ 6
Changes to Figure 4 Caption ........................................................... 7
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
11/2003Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................ 4
Updated Outline Dimensions ....................................................... 15
7/1999Revision 0: Initial Version
Rev. C | Page 2 of 24