2.5 V to 5.5 V, 400 A, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs AD5306/AD5316/AD5326 FEATURES FUNCTIONAL BLOCK DIAGRAM V V A V B DD REF REF AD5306: 4 buffered, 8-bit DACs in 16-lead TSSOP AD5306/AD5316/AD5326 A version: 1 LSB INL B version: 0.625 LSB INL LDAC AD5316: 4 buffered, 10-bit DACs in 16-lead TSSOP INPUT DAC STRING BUFFER V A A version: 4 LSB INL B version: 2.5 LSB INL REGISTER REGISTER OUT DAC A AD5326: 4 buffered, 12-bit DACs in 16-lead TSSOP INPUT DAC STRING SCL A version: 16 LSB INL B version: 10 LSB INL BUFFER V B REGISTER REGISTER OUT DAC B SDA INTERFACE Low power operation: 400 A 3 V, 500 A 5 V LOGIC A1 2 A0 INPUT DAC STRING 2-wire (I C-compatible) serial interface BUFFER V C OUT REGISTER REGISTER DAC C LDAC 2.5 V to 5.5 V power supply INPUT DAC Guaranteed monotonic by design over all codes STRING BUFFER V D REGISTER REGISTER OUT DAC D Power-down to 90 nA 3 V, 300 nA 5 V (PD pin or bit) POWER-ON POWER-DOWN Double-buffered input logic RESET LOGIC Buffered/unbuffered reference input options V D V C REF REF PD GND Output range: 0 V to VREF or 0 V to 2 VREF Figure 1. Power-on reset to 0 V Simultaneous update of outputs (LDAC pin) Software clear facility GENERAL DESCRIPTION Data readback facility 1 The AD5306/AD5316/AD5326 are quad 8-/10-/12-bit buffered On-chip rail-to-rail output buffer amplifiers voltage output DACs in 16-lead TSSOP packages that operate Temperature range 40C to +105C from a single 2.5 V to 5.5 V supply, consuming 500 A at 3 V. Their on-chip output amplifiers allow rail-to-rail output swing APPLICATIONS with a slew rate of 0.7 V/s. A 2-wire serial interface, which Portable battery-powered instruments operates at clock rates up to 400 kHz, is used. This interface is Digital gain and offset adjustment SMBus-compatible at VDD < 3.6 V. Multiple devices can be Programmable voltage and current sources placed on the same bus. Programmable attenuators Each DAC has a separate reference input that can be configured Industrial process control as buffered or unbuffered. The outputs of all DACs can be updated simultaneously using the asynchronous input. LDAC The parts incorporate a power-on reset circuit that ensures the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. The software clear function clears all DACs to 0 V. The parts contain a power-down feature that reduces the current consumption of the device to 300 nA 5 V (90 nA 3 V). All three parts have the same pinout, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board. 1 Protected by U.S. Patent Numbers 5,969,657 and 5,684,481. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved. 02066-001AD5306/AD5316/AD5326 TABLE OF CONTENTS Specifications..................................................................................... 3 Multiple DAC Write Sequence ................................................. 17 AC Characteristics........................................................................ 5 Multiple DAC Readback Sequence .......................................... 17 Timing Characteristics ................................................................ 6 Write Operation.......................................................................... 18 Absolute Maximum Ratings............................................................ 7 Read Operation........................................................................... 18 ESD Caution.................................................................................. 7 Double-Buffered Interface ........................................................ 19 Pin Configuration and Function Descriptions............................. 8 LDAC Load DAC Input ............................................................. 19 Terminology ...................................................................................... 9 Power-Down Mode.................................................................... 19 Typical Performance Characteristics ........................................... 11 Applications..................................................................................... 20 Functional Description .................................................................. 15 Typical Application Circuit....................................................... 20 Digital-to-Analog Section ......................................................... 15 Driving VDD from the Reference Voltage ................................ 20 Resistor String............................................................................. 15 Bipolar Operation Using the AD5306/AD5316/AD5326..... 20 DAC Reference Inputs ............................................................... 15 Multiple Devices on One Bus ................................................... 20 Output Amplifier........................................................................ 15 AD5306/AD5316/AD5326 as a Digitally Programmable Window Detector....................................................................... 21 Power-On Reset .......................................................................... 16 Coarse and Fine Adjustment Using the Serial Interface ............................................................................ 16 AD5306/AD5316/AD5326 ....................................................... 21 Read/Write Sequence................................................................. 16 Power Supply Decoupling ............................................................. 22 Pointer Byte Bits ......................................................................... 16 Outline Dimensions ....................................................................... 24 Input Shift Register..................................................................... 16 Ordering Guide .......................................................................... 24 Default Readback Conditions................................................... 17 REVISION HISTORY 8/05Rev. E to Rev. F 8/03Rev. B to Rev. C Replaced Figure 22 ......................................................................... 13 Added A Version ................................................................Universal Changes to Bipolar Operation Changes to FEATURES ....................................................................1 Using the AD5306/AD5316/AD5326 Section........................ 20 Changes to SPECIFICATIONS .......................................................2 Changes to Ordering Guide .......................................................... 24 Changes to ABSOLUTE MAXIMUM RATINGS.........................5 Edits to ORDERING GUIDE ..........................................................5 5/05Rev. D to Rev. E Changes to TPC 21......................................................................... 11 Changes to Table 1............................................................................ 3 Added OCTALS section to Table I............................................... 18 11/04Rev. C to Rev. D Updated OUTLINE DIMENSIONS ............................................ 19 Change to Figure 31 ....................................................................... 16 4/01Rev. A to Rev. B Changes to Pointer Byte Section................................................... 16 Edit to Figure 6 ............................................................................... 13 Change to Figure 32 ....................................................................... 17 Edits to RIGHT/LEFT section of Pointer Byte Bits section...... 13 Edits to Input Shift Register section ............................................ 13 Edits to Figure 7.............................................................................. 13 Edits to Figure 8.............................................................................. 14 Edits to Figure 9.............................................................................. 14 Edit to Figure 12 ............................................................................. 16 2/01Rev. 0 to Rev. A 6/00Revision 0: Initial Version Rev. F Page 2 of 24