Quad, 10-Bit nanoDAC with 2 ppm/C 2 Reference, I C Interface Data Sheet AD5316R FEATURES FUNCTIONAL BLOCK DIAGRAM V GND V DD REF Low drift 2.5 V on-chip reference: 2 ppm/C typical Tiny package: 3 mm 3 mm, 16-lead LFCSP AD5316R 2.5V REFERENCE TUE: 0.1% of FSR maximum V LOGIC Offset error: 1.5 mV maximum INPUT DAC STRING V A OUT DAC A REGISTER REGISTER Gain error: 0.1% of FSR maximum SCL BUFFER High drive capability: 20 mA, 0.5 V from supply rails STRING INPUT DAC V B OUT REGISTER REGISTER DAC B SDA User-selectable gain of 1 or 2 (GAIN pin) BUFFER Reset to zero scale or midscale (RSTSEL pin) STRING INPUT DAC A1 V C OUT REGISTER REGISTER DAC C 1.8 V logic compatibility BUFFER 2 400 kHz I C-compatible serial interface A0 INPUT DAC STRING 2 V D 4 I C addresses available OUT DAC D REGISTER REGISTER BUFFER Low glitch: 0.5 nV-sec POWER-ON GAIN = POWER- Low power: 3.3 mW at 3 V RESET 1/2 DOWN LOGIC 2.7 V to 5.5 V power supply 40C to +105C temperature range LDAC RESET RSTSEL GAIN Figure 1. APPLICATIONS Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5316R, a member of the nanoDAC family, is a low power, Table 1. Related Devices quad, 10-bit buffered voltage output DAC. The device includes Interface Reference 12-Bit 10-Bit a 2.5 V, 2 ppm/C internal reference (enabled by default) and a SPI Internal AD5684R AD5317R gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V External AD5684 AD5317 2 (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, I C Internal AD5694R 1 is guaranteed monotonic by design, and exhibits less than 0.1% External AD5694 AD5316 FSR gain error and 1.5 mV offset error performance. The device is 1 The AD5316R and the AD5316 are not pin-to-pin or software compatible. available in a 3 mm 3 mm lead lead frame chip scale package (LFCSP) and in a thin shrink small outline package (TSSOP). PRODUCT HIGHLIGHTS The AD5316R also incorporates a power-on reset circuit and a RSTSEL pin. The RSTSEL pin ensures that the DAC outputs power 1. Precision DC Performance. up to zero scale or midscale and remain at that level until a valid Total unadjusted error (TUE): 0.1% of FSR maximum write takes place. The device contains a per channel power- Offset error: 1.5 mV maximum down feature that reduces the current consumption of the Gain error: 0.1% of FSR maximum device in power-down mode to 4 A at 3 V. 2. Low Drift 2.5 V On-Chip Reference. 2 ppm/C typical temperature coefficient The AD5316R uses a versatile 2-wire serial interface that operates 5 ppm/C maximum temperature coefficient at clock rates up to 400 kHz and includes a VLOGIC pin intended 3. Two Package Options. for 1.8 V/3 V/5 V logic. 3 mm 3 mm, 16-lead LFCSP 16-lead TSSOP Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 10819-001AD5316R Data Sheet TABLE OF CONTENTS 2 Features .............................................................................................. 1 I C Slave Address ........................................................................ 18 Applications ....................................................................................... 1 Serial Operation ......................................................................... 18 Functional Block Diagram .............................................................. 1 Write Operation.......................................................................... 18 General Description ......................................................................... 1 Read Operation........................................................................... 19 Product Highlights ........................................................................... 1 Multiple DAC Readback Sequence .......................................... 19 Revision History ............................................................................... 2 Power-Down Operation ............................................................ 20 Specifications ..................................................................................... 3 Load DAC (Hardware LDAC Pin) ........................................... 20 AC Characteristics ........................................................................ 4 LDAC Mask Register ................................................................. 21 Timing Characteristics ................................................................ 5 Hardware Reset Pin (RESET) ................................................... 21 Absolute Maximum Ratings ............................................................ 6 Reset Select Pin (RSTSEL) ........................................................ 21 Thermal Resistance ...................................................................... 6 Internal Reference Setup ........................................................... 22 ESD Caution .................................................................................. 6 Solder Heat Reflow ..................................................................... 22 Pin Configurations and Function Descriptions ........................... 7 Long-Term Temperature Drift ................................................. 22 Typical Performance Characteristics ............................................. 8 Thermal Hysteresis .................................................................... 22 Terminology .................................................................................... 14 Applications Information .............................................................. 23 Theory of Operation ...................................................................... 16 Microprocessor Interfacing ....................................................... 23 Digital-to-Analog Converter .................................................... 16 AD5316R to ADSP-BF531 Interface ........................................ 23 Transfer Function ....................................................................... 16 Layout Guidelines....................................................................... 23 DAC Architecture ....................................................................... 16 Galvanically Isolated Interface ................................................. 23 Serial Interface ............................................................................ 17 Outline Dimensions ....................................................................... 24 Write and Update Commands .................................................. 17 Ordering Guide .......................................................................... 24 REVISION HISTORY 1/2020Rev. C to Rev. D Changes to Figure 35 ...................................................................... 13 Changes to Figure 2 .......................................................................... 5 Changes to Hardware Reset (RESET) Section ............................ 21 Changes to Figure 11 Caption and Figure 12 Caption ................ 9 Added Long-Term Temperature Drift Section and Figure 47 Changes to Figure 38 Caption ....................................................... 13 Renumbered Sequentially ............................................................. 22 Changed Digital-to-Analog Converter Section to Digital-to- Changes to Ordering Guide .......................................................... 24 Analog Converter (DAC) Section ................................................ 16 Changes to Serial Interface Section .............................................. 17 2/2014Rev. A to Rev. B Updated Outline Dimensions ....................................................... 24 Change to Table 2 .............................................................................. 3 Change to Table 7 .............................................................................. 9 5/2017Rev. B to Rev. C Deleted Figure 7, Renumbered Sequentially ................................. 8 Changes to Features Section............................................................ 1 Deleted Long-Term Temperature Drift Section and Changes to Table 2 Summary .......................................................... 3 Figure 48 .......................................................................................... 22 Changes to Table 3 ............................................................................ 4 Changes to Table 4 Summary .......................................................... 5 7/2012Rev. 0 to Rev. A Changes to Table 5 ............................................................................ 6 Change to Features Section .............................................................. 1 RESET Changes to VLOGIC Pin Description and Pin Description, Change to Relative Accuracy Parameter in Table 2 ...................... 3 Table 7 ................................................................................................ 7 Change to Differential Nonlinearity Parameter in Table 2 .......... 3 Changes to Figure 13 to Figure 16 .................................................. 9 Changes to Ordering Guide .......................................................... 24 Changes to Figure 17 to Figure 21 ................................................ 10 Changes to Figure 27 ...................................................................... 11 7/2012Revision 0: Initial Version Changes to Figure 34 ...................................................................... 12 Rev. D Page 2 of 24