2.5 V to 5.5 V, 400 A, Quad Voltage Output, 8-/10-/12-Bit DACs in 16-Lead TSSOP Data Sheet AD5307/AD5317/AD5327 FEATURES GENERAL DESCRIPTION AD5307: 4 buffered 8-bit DACs in 16-lead TSSOP 1 The AD5307/AD5317/AD5327 are quad 8-,10-,12-bit buffered A version: 1 LSB INL B version: 0.625 LSB INL voltage-output DACs in 16-lead TSSOP that operate from single AD5317: 4 buffered 10-bit DACs in 16-lead TSSOP 2.5 V to 5.5 V supplies and consume 400 A at 3 V. Their on- A version: 4 LSB INL B version: 2.5 LSB INL chip output amplifiers allow the outputs to swing rail-to-rail with AD5327: 4 buffered 12-bit DACs in 16-lead TSSOP a slew rate of 0.7 V/s. The AD5307/AD5317/AD5327 utilize A version: 16 LSB INL B version: 10 LSB INL versatile 3-wire serial interfaces that operate at clock rates up to Low power operation: 400 A 3 V, 500 A 5 V 2.5 V to 5.5 V power supply 30 MHz these parts are compatible with standard SPI, QSPI, Guaranteed monotonic by design over all codes MICROWIRE, and DSP interface standards. LDAC Power down to 90 nA 3 V, 300 nA 5 V ( pin) The references for the four DACs are derived from two reference Double-buffered input logic pins (one per DAC pair). These reference inputs can be configured Buffered/unbuffered reference input options as buffered or unbuffered inputs. Each part incorporates a power- Output range: 0 V to VREF or 0 V to 2 VREF Power-on reset to 0 V on reset circuit, ensuring that the DAC outputs power up to 0 V LDAC Simultaneous update of outputs ( pin) and remain there until a valid write to the device takes place. Asynchronous clear facility (CLR pin) CLR There is also an asynchronous active low pin that clears all Low power, SPI-, QSPI-, MICROWIRE-, and DSP- DACs to 0 V. The outputs of all DACs can be updated simul- compatible 3-wire serial interface LDAC taneously using the asynchronous input. Each part SDO daisy-chaining option contains a power-down feature that reduces the current On-chip rail-to-rail output buffer amplifiers consumption of the device to 300 nA 5 V (90 nA 3 V). The Temperature range of 40C to +105C parts can also be used in daisy-chaining applications using the APPLICATIONS SDO pin. Portable battery-powered instruments Digital gain and offset adjustment All three parts are offered in the same pinout, allowing users to Programmable voltage and current sources select the amount of resolution appropriate for their application Programmable attenuators without redesigning their circuit board. Industrial process control FUNCTIONAL BLOCK DIAGRAM V V AB DD REF AD5307/AD5317/AD5327 GAIN-SELECT LOGIC LDAC INPUT DAC STRING V A BUFFER OUT REGISTER REGISTER DAC A SCLK INPUT DAC STRING V B BUFFER OUT REGISTER REGISTER DAC B INTERFACE SYNC LOGIC INPUT DAC STRING V C BUFFER OUT REGISTER REGISTER DAC C DIN INPUT DAC STRING V D BUFFER OUT REGISTER REGISTER DAC D SDO POWER-ON POWER-DOWN RESET LOGIC DCEN LDAC CLR V CD PD GND REF Figure 1. 1 Patents pending. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20002016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 02067-001AD5307/AD5317/AD5327 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 17 Applications ....................................................................................... 1 Control Bits ................................................................................. 17 General Description ......................................................................... 1 Low Power Serial Interface ....................................................... 18 Functional Block Diagram .............................................................. 1 Daisy Chaining ........................................................................... 18 Revision History ............................................................................... 2 Double-Buffered Interface ........................................................ 18 Specif icat ions ..................................................................................... 3 LDAC Load DAC Input ( ) .......................................................... 18 AC Characteristics ........................................................................ 5 Power-Down Mode .................................................................... 18 Timing Characteristics ................................................................ 5 Microprocessor Interfacing ....................................................... 19 Absolute Maximum Ratings ............................................................ 7 Applicat ions ..................................................................................... 20 ESD Caution .................................................................................. 7 Typical Application Circuit ....................................................... 20 Pin Configuration and Function Descriptions ............................. 8 Driving VDD from the Reference Voltage ................................ 20 Typical Performance Characteristics ............................................. 9 Bipolar Operation....................................................................... 20 Terminology .................................................................................... 13 Opto-Isolated Interface for Process-Control Applications ... 21 Transfer Function ........................................................................... 14 Decoding Multiple AD5307/AD5317/AD5327 Devices ....... 21 Functional Description .................................................................. 15 AD5307/AD5317/AD5327 as Digitally Programmable Window Detectors ..................................................................... 21 Digital-to-Analog Section ......................................................... 15 Daisy Chaining ........................................................................... 22 Resistor String ............................................................................. 15 Power Supply Bypassing and Grounding ................................ 22 DAC Reference Inputs ............................................................... 15 Outline Dimensions ....................................................................... 24 Output Amplifier ........................................................................ 16 Ordering Guide .......................................................................... 25 Power-On Reset .......................................................................... 16 Serial Interface ................................................................................ 17 REVISION HISTORY 12/2016Rev. C to Rev. D 8/2003Rev. 0 to Rev. A Change to Input Current Parameter, Table 1 ................................ 4 Added A Version ................................................................ Universal Change to Table 7 ........................................................................... 23 Changes to Features .......................................................................... 1 Changes to Ordering Guide .......................................................... 25 Changes to Specifications ................................................................. 2 Changes to Absolute Maximum Ratings ........................................ 6 3/2006Rev. B to Rev. C Changes to Ordering Guide ............................................................. 6 Changes to Table 3 ............................................................................ 5 Changes to TPC 21 ......................................................................... 12 Changes to Ordering Guide .......................................................... 25 Added Octals section to Table II .................................................. 20 Updated Outline Dimensions ....................................................... 21 10/2005Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Bipolar Operation Section ........................................ 21 Changes to Ordering Guide .......................................................... 25 Rev. D Page 2 of 28