2.5 V to 5.5 V, 500 A, Quad Voltage Output 12-Bit DAC in 10-Lead Package Enhanced Product AD5324-EP FEATURES GENERAL DESCRIPTION 1 The AD5324-EP is a quad 12-bit buffered voltage output Enhanced product features Supports defense and aerospace applications (AQEC) digital-to-analog converter (DAC) in a 10-lead MSOP package Military temperature range (55C to +125C) that operates from a single 2.5 V to 5.5 V supply, consuming Controlled manufacturing baseline 500 A at 3 V. The on-chip output amplifiers allows rail-to-rail One assembly/test site output swing to be achieved with a slew rate of 0.7 V/s. A 3-wire One fabrication site serial interface is used it operates at clock rates up to 30 MHz Enhanced product change notification and is compatible with standard serial peripheral interface (SPI), Qualification data available on request QSPI, MICROWIRE, and DSP interface standards. Four buffered 12-Bit DACs in 10-lead MSOP The references for the four DACs are derived from one reference S Version: 10 LSB INL pin. The outputs of all DACs can be updated simultaneously using Low power operation: 500 A at 3 V, 600 A at 5 V the software LDAC function. The part incorporates a power-on 2.5 V to 5.5 V power supply reset circuit and ensures that the DAC outputs power up to 0 V Guaranteed monotonic by design over all codes and remains there until a valid write takes place to the device. Power-down to 80 nA at 3 V, 200 nA at 5 V The part contains a power-down feature that reduces the current Double-buffered input logic consumption of the device to 200 nA at 5 V (80 nA at 3 V). Output range: 0 V to V REF The low power consumption of this part in normal operation Power-on reset to 0 V makes it ideally suited to portable battery-operated equipment. LDAC Simultaneous update of outputs ( function) The power consumption is 3 mW at 5 V, and 1.5 mW at 3 V, On-chip, rail-to-rail output buffer amplifiers reducing to 1 W in power-down mode. Temperature range 55C to +125C Full details about this enhanced product are available in the APPLICATIONS AD5324 data sheet, which must be consulted in conjunction Portable battery-powered instruments with this data sheet. Digital gain and offset adjustment Programmable voltage and current sources 1 Protected by U.S. Patent No. 5,969,657. Programmable attenuators Industrial process control FUNCTIONAL BLOCK DIAGRAM V REFIN DD AD5324-EP LDAC BUFFER INPUT DAC STRING V A OUT REGISTER REGISTER DAC A BUFFER SCLK INPUT DAC STRING V B OUT REGISTER REGISTER DAC B BUFFER SYNC INPUT DAC STRING V C OUT REGISTER REGISTER DAC C DIN BUFFER INPUT DAC STRING V D OUT REGISTER REGISTER DAC D POWER-ON RESET POWER-DOWN LOGIC GND Figure 1. Rev. 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INTERFACE LOGIC 08 97 1-0 01AD5324-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Timing Characteristics .................................................................5 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................6 General Description ......................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions ..............................7 Revision History ............................................................................... 2 Typical Performance Characteristics ..............................................8 Specif icat ions ..................................................................................... 3 Outline Dimensions ....................................................................... 11 AC Characteristics ........................................................................ 4 Ordering Guide .......................................................................... 11 REVISION HISTORY 6/2019Rev. 0 to Rev. A Changes to Patent Information ....................................................... 1 Changes to Offset Error Parameter, Table 1 and Gain Error Parameter, Table 1 ............................................................................. 3 Changes to Peak Temperature Parameter, Table 4 ....................... 6 Updated Outline Dimensions ....................................................... 11 4/2010Revision 0: Initial Version Rev. A Page 2 of 11