2.5 V to 5.5 V, 230 A, Parallel Interface a Dual Voltage-Output 8-/10-/12-Bit DACs AD5332/AD5333/AD5342/AD5343* FEATURES GENERAL DESCRIPTION AD5332: Dual 8-Bit DAC in 20-Lead TSSOP The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and AD5333: Dual 10-Bit DAC in 24-Lead TSSOP 12-bit DACs. They operate from a 2.5 V to 5.5 V supply con- AD5342: Dual 12-Bit DAC in 28-Lead TSSOP suming just 230 A at 3 V, and feature a power-down pin, PD AD5343: Dual 12-Bit DAC in 20-Lead TSSOP that further reduces the current to 80 nA. These devices incor- Low Power Operation: 230 A 3 V, 300 A 5 V porate an on-chip output buffer that can drive the output to via PD Pin both supply rails, while the AD5333 and AD5342 allow a choice Power-Down to 80 nA 3 V, 200 nA 5 V of buffered or unbuffered reference input. 2.5 V to 5.5 V Power Supply The AD5332/AD5333/AD5342/AD5343 have a parallel interface. Double-Buffered Input Logic CS selects the device and data is loaded into the input registers Guaranteed Monotonic by Design Over All Codes on the rising edge of WR. Buffered/Unbuffered Reference Input Options The GAIN pin on the AD5333 and AD5342 allows the output Output Range: 0V or 02 V REF REF range to be set at 0 V to V or 0 V to 2 V . REF REF Power-On Reset to Zero Volts Simultaneous Update of DAC Outputs via LDAC Pin Input data to the DACs is double-buffered, allowing simultaneous Asynchronous CLR Facility update of multiple DACs in a system using the LDAC pin. Low Power Parallel Data Interface An asynchronous CLR input is also provided, which resets the On-Chip Rail-to-Rail Output Buffer Ampliers contents of the Input Register and the DAC Register to all zeros. Temperature Range: 40 C to +105 C These devices also incorporate a power-on reset circuit that ensures APPLICATIONS that the DAC output powers on to 0 V and remains there until Portable Battery-Powered Instruments valid data is written to the device. Digital Gain and Offset Adjustment The AD5332/AD5333/AD5342/AD5343 are available in Thin Programmable Voltage and Current Sources Shrink Small Outline Packages (TSSOP). Programmable Attenuators Industrial Process Control AD5332 FUNCTIONAL BLOCK DIAGRAM (Other Diagrams Inside) V A V REF DD POWER-ON AD5332 RESET DAC INPUT DB 8-BIT 7 . V A REGISTER BUFFER REGISTER OUT . DAC . DB 0 INTER- FACE LOGIC CS INPUT DAC 8-BIT BUFFER V B REGISTER OUT REGISTER DAC WR A0 RESET POWER-DOWN CLR LOGIC LDAC V B GND PD REF *Protected by U.S. Patent Number 5,969,657 . REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: AD5332/AD5333/AD5342/AD5343SPECIFICATIONS (V = 2.5 V to 5.5 V, V = 2 V. R = 2 k to GND C =200 pF to GND all specications T to T unless otherwise noted.) DD REF L L MIN MAX 2 B Version 1 Parameter Min Typ Max Unit Conditions/Comments 3, 4 DC PERFORMANCE AD5332 Resolution 8 Bits Relative Accuracy 0.15 1 LSB Differential Nonlinearity 0.02 0.25 LSB Guaranteed Monotonic By Design Over All Codes AD5333 Resolution 10 Bits Relative Accuracy 0.5 4 LSB Differential Nonlinearity 0.05 0.5 LSB Guaranteed Monotonic By Design Over All Codes AD5342/AD5343 Resolution 12 Bits Relative Accuracy 2 16 LSB Differential Nonlinearity 0.2 1 LSB Guaranteed Monotonic By Design Over All Codes Offset Error 0.4 3 % of FSR Gain Error 0.15 1 % of FSR 5 Lower Deadband 10 60 mV Lower Deadband Exists Only if Offset Error Is Negative Upper Deadband 10 60 mV V = 5 V. Upper Deadband Exists Only if V V DD REF = DD 6 Offset Error Drift 12 ppm of FSR/C 6 Gain Error Drift 5 ppm of FSR/C 6 DC Power Supply Rejection Ratio 60 dB V = 10% DD 6 DC Crosstalk 200 VR = 2 k to GND, 2 k to V C = 200 pF to GND L DD L Gain = 0 6 DAC REFERENCE INPUT V Input Range 1 V V Buffered Reference (AD5333 and AD5342) REF DD 0.25 V V Unbuffered Reference DD V Input Impedance >10 M Buffered Reference (AD5333 and AD5342) REF 180 k Unbuffered Reference. Gain = 1, Input Impedance = R DAC 90 k Unbuffered Reference. Gain = 2, Input Impedance = R DAC Reference Feedthrough 90 dB Frequency = 10 kHz Channel-to-Channel Isolation 90 dB Frequency = 10 kHz (AD5332, AD5333, and AD5342) 6 OUTPUT CHARACTERISTICS 4, 7 Minimum Output Voltage 0.001 V min Rail-to-Rail Operation 4, 7 Maximum Output Voltage V 0.001 V max DD DC Output Impedance 0.5 Short Circuit Current 25 mA V = 5 V DD 16 mA V = 3 V DD Power-Up Time 2.5 s Coming Out of Power-Down Mode. V = 5 V DD 5 s Coming Out of Power-Down Mode. V = 3 V DD 6 LOGIC INPUTS Input Current 1 A V , Input Low Voltage 0.8 V V = 5 V 10% IL DD 0.6 V V = 3 V 10% DD 0.5 V V = 2.5 V DD V , Input High Voltage 2.4 V V = 5 V 10% IH DD 2.1 V V = 3 V 10% DD 2.0 V V = 2.5 V DD Pin Capacitance 3.5 pF POWER REQUIREMENTS V 2.5 5.5 V DD I (Normal Mode) All DACs active and excluding load currents DD V = 4.5 V to 5.5 V 300 450 A Unbuffered Reference. V = V , V = GND. DD IH DD IL V = 2.5 V to 3.6 V 230 350 A I increases by 50 A at V > V 100 mV. DD DD REF DD In Buffered Mode extra current is (5 +V /R ) A. REF DAC I (Power-Down Mode) DD V = 4.5 V to 5.5 V 0.2 1 A DD V = 2.5 V to 3.6 V 0.08 1 A DD NOTES 1 See Terminology section. 2 Temperature range: B Version: 40C to +105C typical specications are at 25C. 3 Linearity is tested using a reduced code range: AD5332 (Code 8 to 255) AD5333 (Code 28 to 1023) AD5342/AD5343 (Code 115 to 4095). 4 DC specications tested with outputs unloaded. 5 This corresponds to x codes. x = Deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 In order for the amplier output to reach its minimum voltage, Offset Error must be negative. In order for the amplier output to reach its maximum voltage, V = V and REF DD Offset plus Gain Error must be positive. Specications subject to change without notice. 2 REV. 0