40-Channel, 14-Bit, Serial Input, Voltage Output DAC AD5371 FEATURES 40-channel DAC in 80-lead LQFP and 100-ball CSP BGA 2.5 V to 5.5 V digital interface Guaranteed monotonic to 14 bits Digital reset (RESET) Maximum output voltage span of 4 V (20 V) Clear function to user-defined SIGGNDx REF Nominal output voltage span of 4 V to +8 V Simultaneous update of DAC outputs Multiple, independent output voltage spans available APPLICATIONS System calibration function allowing user-programmable Level setting in automatic test equipment (ATE) offset and gain Variable optical attenuators (VOA) Channel grouping and addressing features Optical switches Thermal shutdown function Industrial control systems DSP/microcontroller-compatible serial interface Instrumentation SPI/LVDS serial interface FUNCTIONAL BLOCK DIAGRAM DV V V CC DD SS AGND DGND LDAC VREF0 GROUP 0 14 14 14 BUFFER CONTROL OFS0 OFFSET REGISTER REGISTER 8 8 DAC 0 A/B SELECT TO BUFFER OUTPUT BUFFER REGISTER MUX2 AND 14 VOUT0 X2A X1A POWER-DOWN 14 14 14 14 REGISTER DAC 0 REGISTER VOUT1 CONTROL DAC 0 14 REGISTER X1B X2B VOUT2 REGISTER REGISTER 14 14 VOUT3 M REGISTER SPI/LVDS 14 VOUT4 14 SYNC C REGISTER VOUT5 SDI VOUT6 OUTPUT BUFFER SCLK 14 SERIAL X2A AND VOUT7 X1A 14 14 INTERFACE 14 14 REGISTER DAC 7 POWER-DOWN REGISTER SYNC DAC 7 REGISTER CONTROL SIGGND0 14 X1B X2B SDI REGISTER REGISTER 14 14 SCLK M REGISTER 14 SDO 14 VREF1 C REGISTER GROUP 1 BUSY 14 14 BUFFER OFS1 OFFSET REGISTER 8 8 DAC 1 RESET A/B SELECT TO BUFFER OUTPUT BUFFER REGISTER MUX2 CLR AND 14 VOUT8 X2A X1A POWER-DOWN 14 14 14 14 REGISTER DAC 0 REGISTER VOUT9 CONTROL DAC 0 REGISTER STATE 14 X1B X2B VOUT10 MACHINE REGISTER REGISTER 14 14 VOUT11 14 M REGISTER 14 VOUT12 14 C REGISTER VOUT13 VOUT14 OUTPUT BUFFER 14 X2A AND VOUT15 X1A 14 14 14 14 REGISTER DAC 7 POWER-DOWN REGISTER DAC 7 REGISTER CONTROL 14 SIGGND1 X1B X2B REGISTER REGISTER 14 14 M REGISTER 14 14 VREF2 VREF2 SUPPLIES C REGISTER AD5371 GROUP 2 TO GROUP 4 GROUP 2 TO GROUP 4 VOUT16 ARE SAME AS GROUP 1 TO VOUT39 SIGGND2 SIGGND3 SIGGND4 Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20072008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. MUX 1 MUX 1 MUX 1 MUX 1 MUX 2 MUX 2 MUX 2 MUX 2 05814-001AD5371 TABLE OF CONTENTS Features .............................................................................................. 1 Calibration................................................................................... 19 Applications....................................................................................... 1 Additional Calibration............................................................... 19 Functional Block Diagram .............................................................. 1 Reset Function ............................................................................ 20 Revision History ............................................................................... 2 Clear Function ............................................................................ 20 General Description ......................................................................... 3 BUSY LDAC and Functions...................................................... 20 Specifications..................................................................................... 4 Power-Down Mode.................................................................... 20 Performance Specifications......................................................... 4 Thermal Shutdown Function ................................................... 20 AC Characteristics........................................................................ 5 Toggle Mode................................................................................ 21 Timing Characteristics ................................................................ 6 Serial Interface ................................................................................ 22 Absolute Maximum Ratings............................................................ 9 SPI Interface................................................................................ 22 ESD Caution.................................................................................. 9 LVDS Interface............................................................................ 22 Pin Configurations and Function Descriptions ......................... 10 SPI Write Mode .......................................................................... 22 Typical Performance Characteristics ........................................... 13 SPI Readback Mode ................................................................... 23 Terminology .................................................................................... 15 LVDS Operation......................................................................... 23 Theory of Operation ...................................................................... 16 Register Update Rates ................................................................ 23 DAC Architecture....................................................................... 16 Channel Addressing and Special Modes................................. 23 Channel Groups.......................................................................... 16 Special Function Mode.............................................................. 25 A/B Registers and Gain/Offset Adjustment............................ 17 Applications Information .............................................................. 27 Load DAC.................................................................................... 17 Power Supply Decoupling ......................................................... 27 Offset DACs ................................................................................ 17 Power Supply Sequencing ......................................................... 27 Output Amplifier........................................................................ 18 Interfacing Examples ................................................................. 27 Transfer Function ....................................................................... 18 Outline Dimensions....................................................................... 28 Reference Selection .................................................................... 18 Ordering Guide .......................................................................... 28 REVISION HISTORY 3/08Rev. A to Rev. B 11/07Rev. 0 to Rev. A Added Table 1.................................................................................... 3 Reformatted Specifications Table 1.................................................3 Changes to Timing Characteristics Section.................................. 6 Reformatted Specifications Table 2.................................................6 Changes to Absolute Maximum Ratings Section......................... 9 Change to A/B Registers and Gain/Offset Changes to Table 7.......................................................................... 11 Adjustment Section........................................................................ 19 Changes to Figure 16, Figure 18, and Figure 19 ......................... 14 Change to SPI Write Mode Section.............................................. 24 Changes to A/B Registers and Gain/Offset Adjustment Changes to Ordering Guide .......................................................... 31 Section and Load DAC Section .................................................... 17 8/07Revision 0: Initial Version Changes to Transfer Function Section......................................... 18 Changes to Calibration Section .................................................... 19 Changes to Reset Function Section and Clear Function Section.............................................................................................. 20 Changes to Table 9.......................................................................... 20 Changes to Register Update Rates Section.................................. 23 Rev. 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