32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC AD5378 Interface options FEATURES Parallel interface 32-channel DAC in 13 mm 13 mm 108-lead CSPBGA DSP/microcontroller-compatible 3-wire serial interface Guaranteed monotonic to 14 bits 2.5 V to 5.5 V JEDEC-compliant digital levels Buffered voltage outputs SDO daisy-chaining option Output voltage span of 3.5 V VREF(+) Power-on reset Maximum output voltage span of 17.5 V Digital reset (RESET pin and soft reset function) System calibration function allowing user-programmable offset and gain APPLICATIONS Pseudo differential outputs relative to REFGND Clear function to user-defined REFGND (CLR pin) Level setting in automatic test equipment (ATE) Variable optical attenuators (VOAs) Simultaneous update of DAC outputs (LDAC pin) Optical switches DAC increment/decrement mode Industrial control systems Channel grouping and addressing features FUNCTIONAL BLOCK DIAGRAM V V V AGND DGND LDAC V V 1(+) V 1() REFGND A1 CC DD SS BIAS REF REF VBIAS POWER-ON AD5378 RESET CLR RESET DCEN/WR INPUT DAC 14 14 14 14 VOUT 0 DAC 01 SYNC/CS REG REG / / / / 01 01 REG0 VOUT 1 m REG01 REG1 14 / c REG01 DB13 SCLK/DB12 DIN/DB11 INPUT DAC 14 14 14 14 DAC 2 / REG / / REG / DB0 VOUT 2 2 2 m REG2 14 A7 c REG2 / 14 VOUT 3 / A0 VOUT 4 INPUT DAC 14 14 14 14 SER/PAR REG REG DAC 5 / / / / VOUT 5 DIN 5 5 SCLK m REG7 SDO 14 c REG7 / FIFOEN REFGND B1 INPUT DAC REFGND B2 14 14 14 14 VOUT 6 REG REG DAC 67 / / / / REFGND C1 67 67 VOUT 7 REFGND C2 m REG89 VOUT 8 14 c REG89 REFGND D1 / 4 REFGND D2 VOUT 31 BUSY V 2(+) V 2() REFGND A2 REF REF Figure 1. Protected by U.S. Patent No. 5,969,657 and 6,823,416 other patents pending. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20052009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INTERFACE STATE MACHINE 05292-001AD5378 TABLE OF CONTENTS Features .............................................................................................. 1 Reference Selection .................................................................... 19 Applications ....................................................................................... 1 C a l ibr at ion ................................................................................... 20 Functional Block Diagram .............................................................. 1 Clear Function ............................................................................ 20 Revision History ............................................................................... 2 BUSY and LDAC Functions...................................................... 20 General Description ......................................................................... 3 FIFO vs. Non-FIFO Operation ................................................. 21 Specif icat ions ..................................................................................... 4 BUSY Input Function ................................................................ 21 AC Characteristics ........................................................................ 5 Power-On Reset Function ......................................................... 21 Timing Characteristics ..................................................................... 6 RESET Input Function .............................................................. 21 Serial Interface .............................................................................. 6 Increment/Decrement Function .............................................. 21 Parallel Interface ........................................................................... 9 Interfaces.......................................................................................... 22 Absolute Maximum Ratings .......................................................... 11 Parallel Interface ......................................................................... 22 ESD Caution ................................................................................ 11 Serial Interface ............................................................................ 22 Pin Configuration and Function Descriptions ........................... 12 Data Decoding ................................................................................ 24 Typical Performance Characteristics ........................................... 15 Address Decoding .......................................................................... 25 Terminology .................................................................................... 17 Power Supply Decoupling ............................................................. 26 Functional Description .................................................................. 18 Power-On .................................................................................... 26 DAC ArchitectureGeneral ..................................................... 18 Typical Application Circuit ........................................................... 27 Channel Groups .......................................................................... 18 Outline Dimensions ....................................................................... 28 Transfer Function ....................................................................... 18 Ordering Guide .......................................................................... 28 VBIAS Function ............................................................................. 19 REVISION HISTORY 7/09Rev. 0 to Rev. A Changes to Table 15 ........................................................................ 24 4/05Revision 0: Initial Version Rev. A Page 2 of 28