40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC AD5379 Interface options: FEATURES Parallel interface 40-channel DAC in 13 mm 13 mm 108-lead CSPBGA DSP/microcontroller-compatible, 3-wire serial interface Guaranteed monotonic to 14 bits 2.5 V to 5.5 V JEDEC-compliant digital levels Buffered voltage outputs SDO daisy-chaining option Output voltage span of 3.5 V VREF(+) Power-on reset Maximum output voltage span of 17.5 V RESET Digital reset ( pin and soft reset function) System calibration function allowing user-programmable offset and gain Pseudo differential outputs relative to REFGND APPLICATIONS CLR Clear function to user-defined REFGND ( pin) Level setting in automatic test equipment (ATE) LDAC Simultaneous update of DAC outputs ( pin) Variable optical attenuators (VOA) DAC increment/decrement mode Optical switches Channel grouping and addressing features Industrial control systems FUNCTIONAL BLOCK DIAGRAM V V V AGND DGND LDAC V V 1(+) V 1() REFGND A1 CC DD SS BIAS REF REF VBIAS POWER-ON AD5379 RESET CLR RESET FIFOEN DCEN/WR INPUT DAC VOUT0 14 14 14 14 DAC 01 REG REG SYNC/CS / / / / VOUT1 01 01 REG0 m REG01 REG1 14 c REG01 / DB13 SCLK/DB12 INPUT DAC DIN/DB11 14 14 14 14 DAC 2 / REG / / REG / DB0 VOUT2 2 2 m REG2 VOUT3 14 A7 c REG2 / 14 VOUT4 / VOUT5 A0 VOUT6 INPUT DAC 14 14 14 14 SER/PAR REG REG DAC 7 / / / / VOUT7 DIN 7 7 SCLK m REG7 SDO 14 c REG7 / REFGND B1 VOUT8 INPUT DAC REFGND B2 14 14 14 14 DAC 89 REG REG / / / / VOUT9 REFGND C1 89 89 VOUT10 REFGND C2 m REG89 14 c REG89 REFGND D1 / 4 REFGND D2 VOUT39 BUSY V 2(+) V 2() REFGND A2 REF REF Figure 1. AD5379Protected by U.S. Patent No. 5,969,657. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20042009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INTERFACE STATE MACHINE FIFO 03165-001AD5379 TABLE OF CONTENTS Features .............................................................................................. 1 C a l ibr at ion ................................................................................... 20 Applications ....................................................................................... 1 Clear Function ............................................................................ 20 General Description ......................................................................... 3 BUSY and LDAC Functions...................................................... 20 Specif icat ions ..................................................................................... 4 FIFO vs. Non-FIFO Operation ................................................. 21 AC Characteristics ........................................................................ 5 BUSY Input Function ................................................................ 21 Timing Characteristics ..................................................................... 6 Power-On Reset Function ......................................................... 21 Serial Interface .............................................................................. 6 RESET Input Function .............................................................. 21 Parallel Interface ........................................................................... 9 Increment/Decrement Function .............................................. 21 Absolute Maximum Ratings .......................................................... 11 Interfaces.......................................................................................... 22 ESD Caution ................................................................................ 11 Parallel Interface ......................................................................... 22 Pin Configuration and Function Descriptions ........................... 12 Serial Interface ............................................................................ 22 Terminology .................................................................................... 15 Data Decoding ................................................................................ 24 Typical Performance Characteristics ........................................... 16 Address Decoding .......................................................................... 25 Functional Description .................................................................. 18 Power Supply Decoupling ............................................................. 26 DAC ArchitectureGeneral ..................................................... 18 Power-On .................................................................................... 26 Channel Groups .......................................................................... 18 Typical Application Circuit ........................................................... 27 Transfer Function ....................................................................... 18 Outline Dimensions ....................................................................... 28 VBIAS Function ............................................................................. 19 Ordering Guide .......................................................................... 28 Reference Selection .................................................................... 19 REVISION HISTORY 7/09Rev. A t o Rev. B Changes to Table 14 ........................................................................ 24 1/05Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Change to Transfer Function Equation ....................................... 18 4/04Revision 0: Initial Version Rev. B Page 2 of 28