40-Channel, 3 V/5 V, Single-Supply, 12-Bit, denseDAC Data Sheet AD5381 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Channel monitor INL error: 1 LSB max Simultaneous output update via LDAC On-chip 1.25 V/2.5 V, 10 ppm/C reference Clear function to user-programmable code Temperature range: 40C to +85C Amplifier boost mode to optimize slew rate Rail-to-rail output amplifier User-programmable offset and gain adjust Power-down Toggle mode enables square wave generation Package type: 100-lead LQFP (14 mm 14 mm) Thermal monitors User interfaces APPLICATIONS Parallel Variable optical attenuators (VOAs) Serial (SPI-/QSPI-/MICROWIRE-/DSP-compatible, Level setting (ATE) featuring data readback) 2 Optical micro-electro-mechanical systems (MEMs) I C-compatible Control systems Robust 6.5 kV HBM and 2 kV FICDM ESD rating Instrumentation FUNCTIONAL BLOCK DIAGRAM DVDD (3) DGND (3) AVDD (5) AGND (5) DAC GND (5) REFGND REFOUT/REFIN SIGNAL GND (5) PD AD5381 1.25V/2.5V SER/PAR REFERENCE FIFO EN CS/(SYNC/AD0) WR/(DCEN/AD1) 12 12 12 12 INPUT DAC SDO DAC 0 REG0 REG0 VOUT0 DB11/(DIN/SDA) 12 m REG0 DB10/(SCLK/SCL) FIFO 12 2 DB9/(SPI/I C) R c REG0 + DB8 R INTERFACE STATE CONTROL MACHINE 12 12 12 12 LOGIC INPUT DAC + DAC 1 DB0 REG1 REG1 CONTROL VOUT1 LOGIC A5 12 VOUT2 m REG1 A0 12 c REG1 R VOUT3 R REG0 VOUT4 12 12 12 12 INPUT DAC VOUT5 REG1 DAC 6 REG6 REG6 VOUT6 POWER-ON RESET RESET 12 m REG6 BUSY 12 c REG6 R R CLR 12 12 12 12 INPUT DAC VOUT0VOUT38 DAC 7 REG7 REG7 VOUT7 12 VOUT8 m REG7 39-TO-1 12 R c REG7 MUX R VOUT38 5 VOUT39/MON OUT LDAC Figure 1. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 03732-001AD5381 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Hardware Functions ....................................................................... 26 Integrated Functions ........................................................................ 1 Reset Function ............................................................................ 26 Applications ....................................................................................... 1 Asynchronous Clear Function .................................................. 26 Functional Block Diagram .............................................................. 1 BUSY and LDAC Functions...................................................... 26 Revision History ............................................................................... 3 FIFO Operation in Parallel Mode ............................................ 26 General Description ......................................................................... 4 Power-On Reset .......................................................................... 26 Specifications ..................................................................................... 5 Power-Down ............................................................................... 26 AD5381-5 Specifications ............................................................. 5 Interfaces.......................................................................................... 27 AD5381-3 Specifications ............................................................. 7 DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 27 2 AC Characteristics ........................................................................ 8 I C Serial Interface ..................................................................... 29 Timing Characteristics ..................................................................... 9 Parallel Interface ......................................................................... 31 Serial Interface Timing ................................................................ 9 Microprocessor Interfacing ....................................................... 32 2 I C Serial Interface Timing........................................................ 11 Applications Information .............................................................. 34 Parallel Interface Timing ........................................................... 12 Power Supply Decoupling ......................................................... 34 Absolute Maximum Ratings .......................................................... 14 Power Supply Sequencing ......................................................... 34 ESD Caution ................................................................................ 14 Typical Configuration Circuit .................................................. 35 Pin Configuration and Function Descriptions ........................... 15 Monitor Function ....................................................................... 36 Terminology .................................................................................... 18 Toggle Mode Function ............................................................... 36 Typical Performance Characteristics ........................................... 19 Thermal Monitor Function ....................................................... 36 Functional Description .................................................................. 22 Optical Attenuators .................................................................... 37 DAC ArchitectureGeneral ..................................................... 22 Utilizing FIFO ............................................................................. 37 Data Decoding ............................................................................ 22 Outline Dimensions ....................................................................... 38 On-Chip Special Function Registers (SFR) ............................ 23 Ordering Guide .......................................................................... 38 SFR Commands .......................................................................... 23 Rev. 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