32-Channel, 3 V/5 V, Single-Supply, 12-Bit, denseDAC Data Sheet AD5383 FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Channel monitor INL error: 1 LSB max Simultaneous output update via LDAC On-chip 1.25 V/2.5 V, 10 ppm/C reference Clear function to user-programmable code Temperature range: 40C to +85C Amplifier boost mode to optimize slew rate Rail-to-rail output amplifier User programmable offset and gain adjust Power-down mode Toggle mode enables square wave generation Package type: 100-lead LQFP (14 mm 14 mm) Thermal monitor User Interfaces APPLICATIONS Parallel Variable optical attenuators (VOA) Serial (SPI-/QSPI-/MICROWIRE-/DSP-compatible, featuring data readback) Level setting (ATE) 2 I C-compatible Optical microelectro-mechanical systems (MEMS) Robust 6.5 kV HBM and 2 kV FICDM ESD rating Control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM DV (3) AV (4) DGND ( 3) AGND ( 4) DAC GND ( 4) REFGND REFOUT/REFIN SIGNAL GND (4) DD DD PD AD5383 1.25V/2.5V SER/PAR REFERENCE FIFO EN CS/(SYNC/AD0) WR/(DCEN/AD1) 12 12 12 12 INPUT DAC SDO DAC 0 REG 0 REG 0 V 0 OUT DB11/(DIN/SDA) 12 m REG 0 DB10/(SCLK/SCL) FIFO 12 2 DB9/(SPI/I C) R c REG 0 + DB8 R INTERFACE STATE CONTROL MACHINE 12 12 12 12 LOGIC + INPUT DAC DAC 1 DB0 CONTROL REG 1 REG 1 V 1 OUT LOGIC 12 A4 V 2 m REG 1 OUT A0 12 c REG 1 R V 3 OUT R REG 0 V 4 OUT 12 12 12 12 INPUT DAC V 5 REG 1 OUT DAC 6 REG 6 REG 6 V 6 POWER-ON OUT RESET RESET 12 m REG 6 BUSY 12 R c REG 6 R CLR 12 12 12 12 INPUT DAC V 0V 31 OUT OUT DAC 7 REG 7 REG 7 V 7 OUT 12 MON IN1 m REG 7 V 8 OUT 36-TO-1 12 MON IN2 R c REG 7 MUX MON IN3 R MON IN4 V 31 OUT 4 MON OUT LDAC Figure 1. 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Technical Support www.analog.com 03734-001AD5383 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Hardware Functions ....................................................................... 26 Integrated Functions ........................................................................ 1 Reset Function ............................................................................ 26 Applications ....................................................................................... 1 Asynchronous Clear Function .................................................. 26 Functional Block Diagram .............................................................. 1 BUSY LDAC and Functions...................................................... 26 Revision History ............................................................................... 3 FIFO Operation in Parallel Mode ............................................ 26 General Description ......................................................................... 4 Power-On Reset .......................................................................... 26 Specifications ..................................................................................... 5 Power-Down ............................................................................... 26 AD5383-5 Specifications ............................................................. 5 Interfaces.......................................................................................... 27 AD5383-3 Specifications ............................................................. 7 DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 27 2 AC Characteristics ........................................................................ 8 I C Serial Interface ..................................................................... 29 Timing Characteristics ..................................................................... 9 Parallel Interface ......................................................................... 31 Serial Interface Timing ................................................................ 9 Microprocessor Interfacing ....................................................... 32 2 I C Serial Interface Timing........................................................ 11 Applications Information .............................................................. 34 Parallel Interface Timing ........................................................... 12 Power Supply Decoupling ......................................................... 34 Absolute Maximum Ratings .......................................................... 14 Power Supply Sequencing ......................................................... 34 ESD Caution ................................................................................ 14 Typical Configuration Circuit .................................................. 35 Pin Configuration and Function Descriptions ........................... 15 Channel Monitor Function ....................................................... 36 Terminology .................................................................................... 18 Toggle Mode Function ............................................................... 36 Typical Performance Characteristics ........................................... 19 Thermal Monitor Function ....................................................... 36 Functional Description .................................................................. 22 Optical Attenuators .................................................................... 37 DAC ArchitectureGeneral ..................................................... 22 Utilizing the FIFO ...................................................................... 38 Data Decoding ............................................................................ 22 Outline Dimensions ....................................................................... 39 On-Chip Special Function Registers (SFR) ............................ 23 Ordering Guide .......................................................................... 39 SFR Commands .......................................................................... 23 Rev. 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